src/mainboard/intel/strago/smihandler.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <arch/io.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include "ec.h"
   8
   9 #include <ec/google/chromeec/ec.h>
  10 #include <elog.h>
  11
  12 #include <soc/nvs.h>
  13 #include <soc/pm.h>
  14 #include <soc/gpio.h>
  15
  16 #include "onboard.h"
  17
  18 /* The wake gpio is SUS_GPIO[0]. */
  19 #define WAKE_GPIO_EN SUS_GPIO_EN0
  20
  21 int mainboard_io_trap_handler(int smif)
  22 {
  23         switch (smif) {
  24         case 0x99:
  25                 printk(BIOS_DEBUG, "Sample\n");
  26                 gnvs->smif = 0;
  27                 break;
  28         default:
  29                 return 0;
  30         }
  31
  32         /*
  33          * On success, the IO Trap Handler returns 0
  34          * On failure, the IO Trap Handler returns a value != 0
  35          *
  36          * For now, we force the return value to 0 and log all traps to
  37          * see what's going on.
  38          */
  39         //gnvs->smif = 0;
  40         return 1;
  41 }
  42
  43 static uint8_t mainboard_smi_ec(void)
  44 {
  45         uint8_t cmd = google_chromeec_get_event();
  46         uint16_t pmbase = get_pmbase();
  47         uint32_t pm1_cnt;
  48
  49         /* Log this event */
  50         if (cmd)
  51                 elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
  52
  53         switch (cmd) {
  54         case EC_HOST_EVENT_LID_CLOSED:
  55                 printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
  56
  57                 /* Go to S5 */
  58                 pm1_cnt = inl(pmbase + PM1_CNT);
  59                 pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
  60                 outl(pm1_cnt, pmbase + PM1_CNT);
  61                 break;
  62         }
  63
  64         return cmd;
  65 }
  66
  67 /*
  68  * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
  69  * this includes the enable bits in the lower 16 bits.
  70  */
  71 void mainboard_smi_gpi(uint32_t alt_gpio_smi)
  72 {
  73         if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
  74                 /* Process all pending events */
  75                 while (mainboard_smi_ec() != 0)
  76                         ;
  77         }
  78 }
  79
  80 void mainboard_smi_sleep(uint8_t slp_typ)
  81 {
  82         /* Disable USB charging if required */
  83         switch (slp_typ) {
  84         case ACPI_S3:
  85                 if (gnvs->s3u0 == 0)
  86                         google_chromeec_set_usb_charge_mode(
  87                                 0, USB_CHARGE_MODE_DISABLED);
  88                 if (gnvs->s3u1 == 0)
  89                         google_chromeec_set_usb_charge_mode(
  90                                 1, USB_CHARGE_MODE_DISABLED);
  91
  92                 /* Enable wake events */
  93                 google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
  94                 /* Enable wake pin in GPE block. */
  95                 enable_gpe(WAKE_GPIO_EN);
  96                 break;
  97         case ACPI_S5:
  98                 if (gnvs->s5u0 == 0)
  99                         google_chromeec_set_usb_charge_mode(
 100                                 0, USB_CHARGE_MODE_DISABLED);
 101                 if (gnvs->s5u1 == 0)
 102                         google_chromeec_set_usb_charge_mode(
 103                                 1, USB_CHARGE_MODE_DISABLED);
 104
 105                 /* Enable wake events */
 106                 google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
 107                 break;
 108         }
 109
 110         /* Disable SCI and SMI events */
 111         google_chromeec_set_smi_mask(0);
 112         google_chromeec_set_sci_mask(0);
 113
 114         /* Clear pending events that may trigger immediate wake */
 115         while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
 116                 ;
 117
 118         /* Set LPC lines to low power in S3/S5. */
 119         if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
 120                 lpc_set_low_power();
 121 }
 122
 123 int mainboard_smi_apmc(uint8_t apmc)
 124 {
 125         switch (apmc) {
 126         case APM_CNT_ACPI_ENABLE:
 127                 google_chromeec_set_smi_mask(0);
 128                 /* Clear all pending events */
 129                 while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
 130                         ;
 131                 google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 132                 break;
 133         case APM_CNT_ACPI_DISABLE:
 134                 google_chromeec_set_sci_mask(0);
 135                 /* Clear all pending events */
 136                 while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
 137                         ;
 138                 google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
 139                 break;
 140         }
 141         return 0;
 142 }