src/mainboard/lenovo/g505s/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <Porting.h>
   4 #include <AGESA.h>
   5
   6 #include <northbridge/amd/agesa/state_machine.h>
   7 #include <PlatformMemoryConfiguration.h>
   8
   9 /*
  10  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
  11  *
  12  * Lane Id
  13  * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
  14  * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
  15  * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
  16  * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
  17  * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
  18  * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
  19  * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
  20  * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
  21  * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
  22  * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
  23  * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
  24  * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
  25  * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
  26  * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
  27  * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
  28  * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
  29  * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
  30  * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
  31  * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
  32  * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
  33  * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
  34  * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
  35  * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
  36  * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
  37  * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
  38  * 25 DP0_TX[P,N]1
  39  * 26 DP0_TX[P,N]2
  40  * 27 DP0_TX[P,N]3
  41  * 28 DP1_TX[P,N]0
  42  * 29 DP1_TX[P,N]1
  43  * 30 DP1_TX[P,N]2
  44  * 31 DP1_TX[P,N]3
  45  * 32 DP2_TX[P,N]0
  46  * 33 DP2_TX[P,N]1
  47  * 34 DP2_TX[P,N]2
  48  * 35 DP2_TX[P,N]3
  49  * 36 DP2_TX[P,N]4
  50  * 37 DP2_TX[P,N]5
  51  * 38 DP2_TX[P,N]6
  52  */
  53
  54 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  55         /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
  56         {
  57                 0,
  58                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
  59                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
  60                                 HotplugDisabled,
  61                                 PcieGenMaxSupported,
  62                                 PcieGenMaxSupported,
  63                                 AspmDisabled, 1)
  64         },
  65         /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
  66         {
  67                 0,
  68                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
  69                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
  70                                 HotplugDisabled,
  71                                 PcieGenMaxSupported,
  72                                 PcieGenMaxSupported,
  73                                 AspmDisabled, 1)
  74         },
  75
  76         /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
  77         {
  78                 0,
  79                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  80                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
  81                                 HotplugDisabled,
  82                                 PcieGenMaxSupported,
  83                                 PcieGenMaxSupported,
  84                                 AspmDisabled, 1)
  85         },
  86
  87         /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
  88         {
  89                 0,
  90                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
  91                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
  92                                 HotplugDisabled,
  93                                 PcieGenMaxSupported,
  94                                 PcieGenMaxSupported,
  95                                 AspmDisabled, 1)
  96         },
  97
  98         /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
  99         {
 100                 0,
 101                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
 102                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
 103                                 HotplugDisabled,
 104                                 PcieGenMaxSupported,
 105                                 PcieGenMaxSupported,
 106                                 AspmDisabled, 1)
 107         },
 108
 109         /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
 110         {
 111                 0,
 112                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
 113                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
 114                                 HotplugDisabled,
 115                                 PcieGenMaxSupported,
 116                                 PcieGenMaxSupported,
 117                                 AspmDisabled, 1)
 118         },
 119
 120         /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 121         {
 122                 DESCRIPTOR_TERMINATE_LIST,
 123                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
 124                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
 125                                 HotplugDisabled,
 126                                 PcieGenMaxSupported,
 127                                 PcieGenMaxSupported,
 128                                 AspmDisabled, 0)
 129         },
 130 };
 131
 132 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 133         /* DP0 to HDMI0/DP */
 134         {
 135                 0,
 136                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
 137                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
 138         },
 139         /* DP1 to FCH */
 140         {
 141                 0,
 142                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
 143                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
 144         },
 145         /* DP2 to HDMI1/DP */
 146         {
 147                 DESCRIPTOR_TERMINATE_LIST,
 148                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
 149                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 150         },
 151 };
 152
 153 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 154         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 155         .SocketId     = 0,
 156         .PciePortList = PortList,
 157         .DdiLinkList  = DdiList,
 158 };
 159
 160 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 161 {
 162         FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
 163         FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
 164         FchReset->Xhci1Enable = FALSE;
 165 }
 166
 167 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 168 {
 169         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 170 }
 171
 172 /*----------------------------------------------------------------------------------------
 173  *                        CUSTOMER OVERRIDES MEMORY TABLE
 174  *----------------------------------------------------------------------------------------
 175  */
 176
 177 /*
 178  * Platform Specific Overriding Table allows IBV/OEM to pass in platform
 179  * information to AGESA
 180  * (e.g. MemClk routing, the number of DIMM slots per channel,...).
 181  * If PlatformSpecificTable is populated, AGESA will base its settings on the
 182  * data from the table. Otherwise, it will use its default conservative settings
 183  */
 184 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 185         NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
 186         NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
 187         MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 188         CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
 189         ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
 190         CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 191
 192         PSO_END
 193 };
 194
 195 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 196 {
 197         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 198 }
 199
 200 void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
 201 {
 202         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 203         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 204 }