src/mainboard/lenovo/g505s/buildOpts.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "mainboard.h"
   4
   5 #include <vendorcode/amd/agesa/f15tn/AGESA.h>
   6
   7 /* Include the files that instantiate the configuration definitions. */
   8 #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
   9 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
  10 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
  11 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
  12 /* AGESA nonsense: the next two headers depend on heapManager.h */
  13 #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
  14 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
  15 /* These tables are optional and may be used to adjust memory timing settings */
  16 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
  17 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
  18
  19 /* Select the CPU family */
  20 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT      TRUE
  21
  22 /* Select the CPU socket type */
  23 #define INSTALL_FS1_SOCKET_SUPPORT              TRUE
  24 #define INSTALL_FP2_SOCKET_SUPPORT              TRUE
  25
  26 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT          TRUE
  27 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT          TRUE
  28 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT           TRUE
  29 //#define BLDOPT_REMOVE_ECC_SUPPORT             TRUE
  30 #define BLDOPT_REMOVE_SRAT                      FALSE
  31 #define BLDOPT_REMOVE_WHEA                      FALSE
  32 #define BLDOPT_REMOVE_CRAT                      TRUE
  33
  34 /* Build configuration values here */
  35 #define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
  36
  37 #define BLDCFG_MEMORY_RDIMM_CAPABLE             FALSE
  38 #define BLDCFG_MEMORY_UDIMM_CAPABLE             TRUE
  39 #define BLDCFG_MEMORY_SODIMM_CAPABLE            TRUE
  40 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING      TRUE
  41 #define BLDCFG_ENABLE_ECC_FEATURE               TRUE
  42 #define BLDCFG_ECC_SYNC_FLOOD                   FALSE
  43
  44 #define BLDCFG_UMA_ALLOCATION_MODE              UMA_SPECIFIED
  45 #define BLDCFG_UMA_ALLOCATION_SIZE              0x2000 /* (0x2000 << 16) = 512M */
  46
  47 #define BLDCFG_IOMMU_SUPPORT                    TRUE
  48
  49 #define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
  50
  51 /*
  52  * The GPIO control is not well documented in AGESA, but is in the BKDG
  53  *
  54  * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route
  55  * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1
  56  * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs
  57  * are mostly in Function1, sometimes Function2.
  58  *
  59  * Note that the GpioOut bit does not mean that the GPIO is an output. That bit
  60  * actually controls the output value, so GpioOut means "default to set".
  61  * PullUpB is an inverted logic, so setting this bit means we're actually
  62  * disabling the internal pull-up. The PullDown bit is NOT inverted logic.
  63  * The output driver can be disabled with the GpioOutEnB bit, which is again,
  64  * inverted logic. To make the list more readable, we define a few local macros
  65  * to state what we mean.
  66  */
  67 #define OUTPUT_HIGH     (GpioOut)
  68 #define OUTPUT_LOW      (0)
  69 #define INPUT           (GpioOutEnB)
  70 #define PULL_UP         (0)
  71 #define PULL_DOWN       (PullDown | PullUpB)
  72 #define PULL_NONE       (PullUpB)
  73
  74 CONST GPIO_CONTROL lenovo_g505s_gpio[] = {
  75         {57, Function1, OUTPUT_HIGH | PULL_NONE},       /* WLAN enable */
  76         {-1}
  77 };
  78 #define BLDCFG_FCH_GPIO_CONTROL_LIST            (lenovo_g505s_gpio)
  79
  80 /*
  81  * These definitions could be moved to a common Hudson header, should we decide
  82  * to provide our own, saner SCI mapping function
  83  */
  84 #define GEVENT_PIN(gpe)         ((gpe) + 0x40)
  85 #define SCI_MAP_OHCI_12_0       0x58
  86 #define SCI_MAP_OHCI_13_0       0x59
  87 #define SCI_MAP_XHCI_10_0       0x78
  88 #define SCI_MAP_PWRBTN          0x73
  89
  90 CONST SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
  91         {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},
  92         {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},
  93         {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},
  94         {SCI_MAP_OHCI_12_0, PME_GPE},
  95         {SCI_MAP_OHCI_13_0, PME_GPE},
  96         {SCI_MAP_XHCI_10_0, PME_GPE},
  97         {SCI_MAP_PWRBTN, PME_GPE},
  98 };
  99 #define BLDCFG_FCH_SCI_MAP_LIST                 (lenovo_g505s_sci_map)
 100
 101 /*
 102  * Process the options...
 103  * This file include MUST occur AFTER the user option selection settings.
 104  * AGESA nonsense: Moving this include up will break AGESA.
 105  */
 106 #include <PlatformInstall.h>