1 /* SPDX-License-Identifier: GPL-2.0-only */
5 /* DefinitionBlock Statement */
13 0x00010001 /* OEM Revision */
15 { /* Start of ASL file */
16 #include <acpi/dsdt_top.asl>
18 /* Globals for the platform */
19 #include "acpi/mainboard.asl"
21 /* Describe the USB Overcurrent pins */
22 #include "acpi/usb_oc.asl"
24 /* PCI IRQ mapping for the Southbridge */
25 #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
27 /* Describe the processor tree (\_SB) */
28 #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
30 /* Describe the supported Sleep States for this Southbridge */
31 #include <southbridge/amd/common/acpi/sleepstates.asl>
33 /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
34 #include "acpi/sleep.asl"
37 /* global utility methods expected within the \_SB scope */
38 #include <arch/x86/acpi/globutil.asl>
40 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
41 #include "acpi/routing.asl"
44 /* Describe the AMD Northbridge */
45 #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
47 /* Describe the AMD Fusion Controller Hub Southbridge */
48 #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
52 /* Describe PCI INT[A-H] for the Southbridge */
53 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
55 } /* End Scope(_SB) */
57 Scope(\_SB.PCI0.LIBR) {
58 #include "acpi/ec.asl"
61 /* Describe SMBUS for the Southbridge */
62 #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
64 /* Define the General Purpose Events for the platform */
65 #include "acpi/gpe.asl"
67 /* Define the Thermal zones and methods for the platform */
68 #include "acpi/thermal.asl"