payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / mainboard / lenovo / g505s / dsdt.asl
blobc7ab79278e58368f622f904a6432fc48fed2acd7
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include "mainboard.h"
5 /* DefinitionBlock Statement */
6 #include <acpi/acpi.h>
7 DefinitionBlock (
8         "dsdt.aml",
9         "DSDT",
10         ACPI_DSDT_REV_2,
11         OEM_ID,
12         ACPI_TABLE_CREATOR,
13         0x00010001              /* OEM Revision */
14         )
15 {       /* Start of ASL file */
16         #include <acpi/dsdt_top.asl>
18         /* Globals for the platform */
19         #include "acpi/mainboard.asl"
21         /* Describe the USB Overcurrent pins */
22         #include "acpi/usb_oc.asl"
24         /* PCI IRQ mapping for the Southbridge */
25         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
27         /* Describe the processor tree (\_SB) */
28         #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
30         /* Describe the supported Sleep States for this Southbridge */
31         #include <southbridge/amd/common/acpi/sleepstates.asl>
33         /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
34         #include "acpi/sleep.asl"
36         Scope(\_SB) {
37                 /* global utility methods expected within the \_SB scope */
38                 #include <arch/x86/acpi/globutil.asl>
40                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
41                 #include "acpi/routing.asl"
43                 Device(PCI0) {
44                         /* Describe the AMD Northbridge */
45                         #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
47                         /* Describe the AMD Fusion Controller Hub Southbridge */
48                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
50                 }
52                 /* Describe PCI INT[A-H] for the Southbridge */
53                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
55         }   /* End Scope(_SB) */
57         Scope(\_SB.PCI0.LIBR) {
58                 #include "acpi/ec.asl"
59         }
61         /* Describe SMBUS for the Southbridge */
62         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
64         /* Define the General Purpose Events for the platform */
65         #include "acpi/gpe.asl"
67         /* Define the Thermal zones and methods for the platform */
68         #include "acpi/thermal.asl"
70 /* End of ASL file */