src/mainboard/msi/ms7721/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pnp_def.h>
   5 #include <device/pnp_ops.h>
   6 #include <device/pnp_type.h>
   7 #include <stdint.h>
   8 #include <amdblocks/acpimmio.h>
   9 #include <superio/fintek/common/fintek.h>
  10 #include <superio/fintek/f71869ad/f71869ad.h>
  11
  12 /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
  13 #define SUPERIO_ADDRESS 0x4e
  14
  15 #define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1)
  16 #define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO)
  17
  18 /* GPIO configuration */
  19 static void gpio_init(pnp_devfn_t dev)
  20 {
  21         pnp_enter_conf_state(dev);
  22         pnp_set_logical_device(dev);
  23         pnp_set_enable(dev, 0);
  24         pnp_write_config(dev, PNP_IDX_IO0, 0x0a); //Base addr high
  25         pnp_write_config(dev, 0x61, 0x00); //Base addr low
  26         pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable
  27         pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data
  28         pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable
  29         pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable
  30         pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select
  31         pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status
  32         pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable
  33         pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data
  34         pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable
  35         pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable
  36         pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data
  37         pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable
  38         pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data
  39         pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable
  40         pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable
  41         pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select
  42         pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status
  43         pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable
  44         pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data
  45         pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable
  46         pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable
  47         pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select
  48         pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status
  49         pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable
  50         pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data
  51         pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable
  52         pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable
  53         pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data
  54         pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable
  55         pnp_set_enable(dev, 1);
  56         pnp_exit_conf_state(dev);
  57 }
  58
  59 static void sbxxx_enable_48mhzout(void)
  60 {
  61         /* most likely programming to 48MHz out signal */
  62         u32 reg32;
  63         reg32 = misc_read32(0x28);
  64         reg32 &= 0xffc7ffff;
  65         reg32 |= 0x00100000;
  66         misc_write32(0x28, reg32);
  67
  68         reg32 = misc_read32(0x40);
  69         reg32 &= ~0x80u;
  70         misc_write32(0x40, reg32);
  71 }
  72
  73 void bootblock_mainboard_early_init(void)
  74 {
  75         /* enable SIO clock */
  76         sbxxx_enable_48mhzout();
  77
  78         /* Initialize GPIO registers */
  79         gpio_init(GPIO_DEV);
  80
  81         /* Enable serial console */
  82         fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  83 }