src/mainboard/msi/ms7721/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* DefinitionBlock Statement */
   4 #include <acpi/acpi.h>
   5 DefinitionBlock (
   6         "dsdt.aml",
   7         "DSDT",
   8         ACPI_DSDT_REV_2,
   9         OEM_ID,
  10         ACPI_TABLE_CREATOR,
  11         0x00010001              /* OEM Revision */
  12         )
  13 {       /* Start of ASL file */
  14         #include <acpi/dsdt_top.asl>
  15         #include <arch/x86/acpi/debug.asl>      /* Include global debug methods if needed */
  16
  17         /* PCI IRQ mapping for the Southbridge */
  18         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  19
  20         /* Describe the processor tree (\_SB) */
  21         #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
  22
  23         /* Describe the supported Sleep States for this Southbridge */
  24         #include <southbridge/amd/common/acpi/sleepstates.asl>
  25
  26         /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
  27         #include "acpi/sleep.asl"
  28
  29         Scope(\_SB) {
  30                 /* global utility methods expected within the \_SB scope */
  31                 #include <arch/x86/acpi/globutil.asl>
  32
  33                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  34                 #include "acpi/routing.asl"
  35
  36                 Device(PCI0) {
  37                         /* Describe the AMD Northbridge */
  38                         #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
  39
  40                         /* Describe the AMD Fusion Controller Hub Southbridge */
  41                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  42                 }
  43
  44                 /* Describe PCI INT[A-H] for the Southbridge */
  45                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  46
  47                 /* Describe USB for the Southbridge */
  48                 #include <southbridge/amd/agesa/hudson/acpi/usb.asl>
  49
  50         }   /* End Scope(_SB)  */
  51
  52         /* Describe SMBUS for the Southbridge */
  53         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  54
  55         /* Define the General Purpose Events for the platform */
  56         #include "acpi/gpe.asl"
  57
  58         /* Define the Thermal zones and methods for the platform */
  59         #include "acpi/thermal.asl"
  60 }
  61 /* End of ASL file */