src/mainboard/msi/ms7721/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/x86/msr.h>
   4 #include <cpu/amd/msr.h>
   5 #include <device/device.h>
   6 #include <southbridge/amd/common/amd_pci_util.h>
   7
   8 static const u8 mainboard_picr_data[] = {
   9         0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  10         0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  11         0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  12         0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  13         0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  14         0x1F, 0x1F, 0x1F, 0x1F
  15 };
  16 static const u8 mainboard_intr_data[0x54] = {
  17         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  18         0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  19         0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  20         0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  21         0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  22         0x10, 0x11, 0x12, 0x13
  23 };
  24
  25 /* PIRQ Setup */
  26 static void pirq_setup(void)
  27 {
  28         intr_data_ptr = mainboard_intr_data;
  29         picr_data_ptr = mainboard_picr_data;
  30 }
  31
  32 /*************************************************
  33  * enable the dedicated function in thatcher board.
  34  *************************************************/
  35 static void mainboard_enable(struct device *dev)
  36 {
  37         msr_t msr;
  38
  39         pirq_setup();
  40
  41         msr = rdmsr(LS_CFG_MSR);
  42         msr.lo &= ~(1 << 28);
  43         wrmsr(LS_CFG_MSR, msr);
  44
  45         msr = rdmsr(DC_CFG_MSR);
  46         msr.lo &= ~(1 << 4);
  47         msr.lo &= ~(1 << 13);
  48         wrmsr(DC_CFG_MSR, msr);
  49
  50         msr = rdmsr(BU_CFG_MSR);
  51         msr.lo &= ~(1 << 23);
  52         wrmsr(BU_CFG_MSR, msr);
  53 }
  54
  55 struct chip_operations mainboard_ops = {
  56         .enable_dev = mainboard_enable,
  57 };