src/mainboard/msi/ms7d25/devicetree.cb

   1 chip soc/intel/alderlake
   2         # FSP configuration
   3
   4         register "eist_enable" = "1"
   5
   6         # Sagv Configuration
   7         register "sagv" = "SaGv_Enabled"
   8         register "RMT" = "0"
   9         register "enable_c6dram" = "1"
  10
  11         register "pmc_gpe0_dw0" = "GPP_J"
  12         register "pmc_gpe0_dw1" = "GPP_VPGIO"
  13         register "pmc_gpe0_dw2" = "GPD"
  14
  15         # USB Configuration
  16         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # USB-C LAN_USB1
  17         register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # MSI MYSTIC LIGHT
  18         register "usb2_ports[2]" = "USB2_PORT_MAX(OC0)" # USB-A LAN_USB1
  19         register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # JUSB5
  20         register "usb2_ports[4]" = "USB2_PORT_MAX(OC3)" # HUB to rear USB 2.0
  21         register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty?
  22         register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4
  23         register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4
  24         register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3
  25         register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3
  26         register "usb2_ports[10]" = "USB2_PORT_MAX(OC0)" # PS2_USB1
  27         register "usb2_ports[11]" = "USB2_PORT_MAX(OC0)" # PS2_USB1
  28         register "usb2_ports[12]" = "USB2_PORT_MAX(OC0)" # HUB to USB 2.0 headers
  29         register "usb2_ports[13]" = "USB2_PORT_MAX(OC6)" # CNVi BT
  30
  31         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
  32         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
  33         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
  34         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
  35         register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
  36         register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
  37         register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
  38         register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
  39         register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
  40         register "usb3_ports[9]" = "USB3_PORT_EMPTY"
  41
  42         # LPC generic I/O ranges
  43         register "gen1_dec" = "0x00fc0201"
  44         register "gen2_dec" = "0x003c0a01"
  45         register "gen3_dec" = "0x000c03f1"
  46         register "gen4_dec" = "0x000c0081"
  47
  48         register "sata_salp_support" = "1"
  49
  50         register "sata_ports_enable" = "{
  51                 [0] = 1,
  52                 [1] = 1,
  53                 [2] = 1,
  54                 [3] = 1,
  55                 [4] = 1,
  56                 [5] = 1,
  57                 [6] = 1,
  58                 [7] = 1,
  59         }"
  60
  61         register "sata_ports_dev_slp" = "{
  62                 [0] = 0,
  63                 [1] = 0,
  64                 [2] = 0,
  65                 [3] = 0,
  66                 [4] = 0,
  67                 [5] = 0,
  68                 [6] = 1,
  69                 [7] = 1,
  70         }"
  71
  72         # HDMI on port B
  73         register "ddi_portB_config" = "1"
  74         register "ddi_ports_config" = "{
  75                 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  76                 [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  77                 [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  78                 [DDI_PORT_2] = DDI_ENABLE_HPD,
  79                 [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  80                 [DDI_PORT_4] = DDI_ENABLE_HPD,
  81         }"
  82
  83         register "hybrid_storage_mode" = "1"
  84         register "dmi_power_optimize_disable" = "1"
  85
  86         # FIVR configuration
  87         register "fivr_rfi_frequency" = "1394"
  88         register "fivr_spread_spectrum" = "FIVR_SS_1_5"
  89         register "ext_fivr_settings" = "{
  90                 .configure_ext_fivr = 1,
  91         }"
  92
  93         device domain 0 on
  94                 subsystemid 0x1462 0x7d25 inherit
  95                 device ref pcie5_0 on
  96                         register "cpu_pcie_rp[CPU_RP(2)]" = "{
  97                                 .clk_src = 0,
  98                                 .clk_req = 0,
  99                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
 100                                 .PcieRpL1Substates = L1_SS_L1_2,
 101                                 .pcie_rp_aspm = ASPM_L0S_L1,
 102                         }"
 103                         smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
 104                                          "PCI_E1" "SlotDataBusWidth16X"
 105                 end
 106                 device ref pcie5_1 off end
 107                 device ref igpu on end
 108                 device ref pcie4_0 on
 109                         register "cpu_pcie_rp[CPU_RP(1)]" = "{
 110                                 .clk_src = 9,
 111                                 .clk_req = 9,
 112                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
 113                                 .PcieRpL1Substates = L1_SS_L1_2,
 114                                 .pcie_rp_aspm = ASPM_L0S_L1,
 115                         }"
 116                         smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 117                                          "M2_1" "SlotDataBusWidth4X"
 118                 end
 119                 device ref crashlog off end
 120                 device ref xhci on end
 121                 device ref cnvi_wifi on
 122                         # Enable CNVi BT
 123                         register "cnvi_bt_core" = "true"
 124                         register "cnvi_bt_audio_offload" = "false"
 125                         chip drivers/wifi/generic
 126                                 register "wake" = "GPE0_PME_B0"
 127                                 register "enable_cnvi_ddr_rfim" = "true"
 128                                 device generic 0 on end
 129                         end
 130                 end
 131                 device ref heci1 on end
 132                 device ref heci2 off end
 133                 device ref ide_r off end
 134                 device ref kt off end
 135                 device ref heci3 off end
 136                 device ref heci4 off end
 137                 device ref sata on end
 138                 device ref pcie_rp1 on
 139                         register "pch_pcie_rp[PCH_RP(1)]" = "{
 140                                 .clk_src = 10,
 141                                 .clk_req = 10,
 142                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
 143                                 .PcieRpL1Substates = L1_SS_L1_2,
 144                                 .pcie_rp_aspm = ASPM_L0S_L1,
 145                         }"
 146                         smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
 147                                          "PCI_E2" "SlotDataBusWidth1X"
 148                 end
 149                 device ref pcie_rp2 on
 150                         register "pch_pcie_rp[PCH_RP(2)]" = "{
 151                                 .clk_src = 17,
 152                                 .clk_req = 17,
 153                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
 154                                 .PcieRpL1Substates = L1_SS_L1_2,
 155                                 .pcie_rp_aspm = ASPM_L0S_L1,
 156                         }"
 157                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
 158                                          "PCI_E4" "SlotDataBusWidth1X"
 159                 end
 160                 device ref pcie_rp3 on
 161                         # i225 Ethernet, Clock PM unsupported, onboard device
 162                         register "pch_pcie_rp[PCH_RP(3)]" = "{
 163                                 .clk_src = 12,
 164                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
 165                                 .PcieRpL1Substates = L1_SS_L1_2,
 166                                 .pcie_rp_aspm = ASPM_L0S_L1,
 167                         }"
 168                 end
 169                 device ref pcie_rp4 off end
 170
 171                 device ref pcie_rp5 on
 172                         register "pch_pcie_rp[PCH_RP(5)]" = "{
 173                                 .clk_src = 15,
 174                                 .clk_req = 15,
 175                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
 176                                 .PcieRpL1Substates = L1_SS_L1_2,
 177                                 .pcie_rp_aspm = ASPM_L0S_L1,
 178                         }"
 179                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
 180                                          "PCI_E3" "SlotDataBusWidth4X"
 181                 end
 182
 183                 device ref pcie_rp9 on
 184                         register "pch_pcie_rp[PCH_RP(9)]" = "{
 185                                 .clk_src = 13,
 186                                 .clk_req = 13,
 187                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
 188                                 .PcieRpL1Substates = L1_SS_L1_2,
 189                                 .pcie_rp_aspm = ASPM_L0S_L1,
 190                         }"
 191                         smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 192                                          "M2_3" "SlotDataBusWidth4X"
 193                 end
 194
 195                 # These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports.
 196                 # There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe
 197                 # 9-12, 21-24 to M2_3 and M2_4 slots
 198                 device ref pcie_rp13 off end
 199                 device ref pcie_rp14 off end
 200                 device ref pcie_rp15 off end
 201                 device ref pcie_rp16 off end
 202                 device ref pcie_rp17 off end
 203                 device ref pcie_rp18 off end
 204                 device ref pcie_rp19 off end
 205                 device ref pcie_rp20 off end
 206
 207                 device ref pcie_rp21 on
 208                         register "pch_pcie_rp[PCH_RP(21)]" = "{
 209                                 .clk_src = 14,
 210                                 .clk_req = 14,
 211                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
 212                                 .PcieRpL1Substates = L1_SS_L1_2,
 213                                 .pcie_rp_aspm = ASPM_L0S_L1,
 214                         }"
 215                         smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 216                                          "M2_4" "SlotDataBusWidth4X"
 217                 end
 218
 219                 device ref pcie_rp25 on
 220                         register "pch_pcie_rp[PCH_RP(25)]" = "{
 221                                 .clk_src = 8,
 222                                 .clk_req = 8,
 223                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
 224                                 .PcieRpL1Substates = L1_SS_L1_2,
 225                                 .pcie_rp_aspm = ASPM_L0S_L1,
 226                         }"
 227                         smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
 228                                          "M2_2" "SlotDataBusWidth4X"
 229                 end
 230                 device ref pch_espi on
 231                         chip superio/nuvoton/nct6687d
 232                                 device pnp 4e.1 off end         # Parallel port
 233                                 device pnp 4e.2 on              # COM1
 234                                         io 0x60 = 0x3f8
 235                                         irq 0x70 = 4
 236                                 end
 237                                 device pnp 4e.3 off end         # COM2, IR
 238                                 device pnp 4e.5 on              # Keyboard
 239                                         io 0x60 = 0x60
 240                                         io 0x62 = 0x64
 241                                         irq 0x70 = 1
 242                                         irq 0x72 = 12
 243                                 end
 244                                 device pnp 4e.6 off end         # CIR
 245                                 device pnp 4e.7 off end         # GPIO0-7
 246                                 device pnp 4e.8 off end         # P80 UART
 247                                 device pnp 4e.9 off end         # GPIO8-9, GPIO1-8 AF
 248                                 device pnp 4e.a on              # ACPI
 249                                         # Vendor firmware did not assign I/O and IRQ
 250                                 end
 251                                 device pnp 4e.b on              # EC
 252                                         io 0x60 = 0xa20
 253                                         # Vendor firmware did not assign IRQ
 254                                 end
 255                                 device pnp 4e.c off end         # RTC
 256                                 device pnp 4e.d off end         # Deep Sleep
 257                                 device pnp 4e.e off end         # TACH/PWM assignment
 258                                 device pnp 4e.f off end         # Function register
 259                         end
 260                 end
 261                 device ref p2sb on end
 262                 device ref hda on
 263                         subsystemid 0x1462 0x9d25
 264                         register "pch_hda_dsp_enable" = "0"
 265                         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 266                         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 267                         register "pch_hda_idisp_codec_enable" = "true"
 268                 end
 269                 device ref smbus on end
 270
 271                 chip drivers/crb
 272                         device mmio 0xfed40000 on end
 273                 end
 274         end
 275 end