src/mainboard/protectli/vault_kbl/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Enable deep Sx states
   4         register "deep_s3_enable_ac" = "0"
   5         register "deep_s3_enable_dc" = "0"
   6         register "deep_s5_enable_ac" = "1"
   7         register "deep_s5_enable_dc" = "1"
   8         register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
   9         register "s0ix_enable" = "1"
  10
  11         register "gpe0_dw0" = "GPP_B"
  12         register "gpe0_dw1" = "GPP_D"
  13         register "gpe0_dw2" = "GPP_E"
  14
  15         register "gen1_dec" = "0x00fc0201"
  16         register "gen2_dec" = "0x007c0a01"
  17         register "gen3_dec" = "0x000c03e1"
  18         register "gen4_dec" = "0x001c02e1"
  19
  20         register "eist_enable" = "1"
  21
  22         # Disable DPTF
  23         register "dptf_enable" = "0"
  24
  25         # Enable SERIRQ continuous
  26         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  27
  28         register "tcc_offset" = "5" # TCC of 95C
  29
  30         # FSP Configuration
  31         register "SataSalpSupport" = "0"
  32         register "DspEnable" = "0"
  33         register "IoBufferOwnership" = "0"
  34         register "SsicPortEnable" = "0"
  35         register "ScsEmmcHs400Enabled" = "0"
  36         register "SkipExtGfxScan" = "1"
  37         register "SaGv" = "SaGv_Enabled"
  38         register "IslVrCmd" = "2"
  39         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  40         register "PmConfigSlpS4MinAssert" = "4"         # 4s
  41         register "PmConfigSlpSusMinAssert" = "1"        # 500ms
  42         register "PmConfigSlpAMinAssert" = "3"          # 2s
  43
  44         # VR Settings Configuration for 4 Domains
  45         #+----------------+-------+-------+-------+-------+
  46         #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
  47         #+----------------+-------+-------+-------+-------+
  48         #| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
  49         #| Psi2Threshold  | 4A    | 5A    | 5A    | 5A    |
  50         #| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
  51         #| Psi3Enable     | 1     | 1     | 1     | 1     |
  52         #| Psi4Enable     | 1     | 1     | 1     | 1     |
  53         #| ImonSlope      | 0     | 0     | 0     | 0     |
  54         #| ImonOffset     | 0     | 0     | 0     | 0     |
  55         #| IccMax         | 7A    | 34A   | 35A   | 35A   |
  56         #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
  57         #| AcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
  58         #| DcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
  59         #+----------------+-------+-------+-------+-------+
  60         #Note: IccMax settings are moved to SoC code
  61         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  62                 .vr_config_enable = 1,
  63                 .psi1threshold = VR_CFG_AMP(20),
  64                 .psi2threshold = VR_CFG_AMP(4),
  65                 .psi3threshold = VR_CFG_AMP(1),
  66                 .psi3enable = 1,
  67                 .psi4enable = 1,
  68                 .imon_slope = 0x0,
  69                 .imon_offset = 0x0,
  70                 .voltage_limit = 1520,
  71         }"
  72
  73         register "domain_vr_config[VR_IA_CORE]" = "{
  74                 .vr_config_enable = 1,
  75                 .psi1threshold = VR_CFG_AMP(20),
  76                 .psi2threshold = VR_CFG_AMP(5),
  77                 .psi3threshold = VR_CFG_AMP(1),
  78                 .psi3enable = 1,
  79                 .psi4enable = 1,
  80                 .imon_slope = 0x0,
  81                 .imon_offset = 0x0,
  82                 .voltage_limit = 1520,
  83         }"
  84
  85         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  86                 .vr_config_enable = 1,
  87                 .psi1threshold = VR_CFG_AMP(20),
  88                 .psi2threshold = VR_CFG_AMP(5),
  89                 .psi3threshold = VR_CFG_AMP(1),
  90                 .psi3enable = 1,
  91                 .psi4enable = 1,
  92                 .imon_slope = 0x0,
  93                 .imon_offset = 0x0,
  94                 .voltage_limit = 1520,
  95         }"
  96
  97         register "domain_vr_config[VR_GT_SLICED]" = "{
  98                 .vr_config_enable = 1,
  99                 .psi1threshold = VR_CFG_AMP(20),
 100                 .psi2threshold = VR_CFG_AMP(5),
 101                 .psi3threshold = VR_CFG_AMP(1),
 102                 .psi3enable = 1,
 103                 .psi4enable = 1,
 104                 .imon_slope = 0x0,
 105                 .imon_offset = 0x0,
 106                 .voltage_limit = 1520,
 107         }"
 108
 109         # Send an extra VR mailbox command for the PS4 exit issue
 110         register "SendVrMbxCmd" = "2"
 111
 112         # Enable SATA ports 1,2
 113         register "SataPortsEnable[0]" = "1"
 114         register "SataPortsEnable[1]" = "1"
 115         register "SataPortsEnable[2]" = "0"
 116         register "SataPortsDevSlp[0]" = "0"
 117         register "SataPortsDevSlp[1]" = "0"
 118
 119         # Enable Root ports. 1-6 for LAN and Root Port 9
 120         register "PcieRpEnable[0]" = "1"
 121         register "PcieRpEnable[1]" = "1"
 122         register "PcieRpEnable[2]" = "1"
 123         register "PcieRpEnable[3]" = "1"
 124         register "PcieRpEnable[4]" = "1"
 125         register "PcieRpEnable[5]" = "1"
 126         register "PcieRpEnable[8]" = "1" # mPCIe WiFi
 127
 128         # Enable Advanced Error Reporting for RP 1-6, 9
 129         register "PcieRpAdvancedErrorReporting[0]" = "1"
 130         register "PcieRpAdvancedErrorReporting[1]" = "1"
 131         register "PcieRpAdvancedErrorReporting[2]" = "1"
 132         register "PcieRpAdvancedErrorReporting[3]" = "1"
 133         register "PcieRpAdvancedErrorReporting[4]" = "1"
 134         register "PcieRpAdvancedErrorReporting[5]" = "1"
 135         register "PcieRpAdvancedErrorReporting[8]" = "1"
 136
 137         # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9
 138         register "PcieRpLtrEnable[0]" = "1"
 139         register "PcieRpLtrEnable[1]" = "1"
 140         register "PcieRpLtrEnable[2]" = "1"
 141         register "PcieRpLtrEnable[3]" = "1"
 142         register "PcieRpLtrEnable[4]" = "1"
 143         register "PcieRpLtrEnable[5]" = "1"
 144         register "PcieRpLtrEnable[8]" = "1"
 145
 146         # Enable RP 9 CLKREQ# support
 147         register "PcieRpClkReqSupport[8]" = "1"
 148         # RP 9 uses CLKREQ0#
 149         register "PcieRpClkReqNumber[8]" = "0"
 150
 151         # Clocks 0-5 for RP 1-6
 152         register "PcieRpClkSrcNumber[0]" = "0"
 153         register "PcieRpClkSrcNumber[1]" = "1"
 154         register "PcieRpClkSrcNumber[2]" = "2"
 155         register "PcieRpClkSrcNumber[3]" = "3"
 156         register "PcieRpClkSrcNumber[4]" = "4"
 157         register "PcieRpClkSrcNumber[5]" = "5"
 158         # RP 9 shares CLKSRC5# with RP 6
 159         register "PcieRpClkSrcNumber[8]" = "5"
 160
 161
 162         # USB 2.0 enable ports 1-8, disable ports 9-12
 163         register "usb2_ports[0]"  = "USB2_PORT_SHORT(OC_SKIP)"  # TYPE-A Port
 164         register "usb2_ports[1]"  = "USB2_PORT_SHORT(OC_SKIP)"  # TYPE-A Port
 165         register "usb2_ports[2]"  = "USB2_PORT_SHORT(OC_SKIP)"  # TYPE-A Port
 166         register "usb2_ports[3]"  = "USB2_PORT_SHORT(OC_SKIP)"  # TYPE-A Port
 167         register "usb2_ports[4]"  = "USB2_PORT_SHORT(OC_SKIP)"  # Type-A Port
 168         register "usb2_ports[5]"  = "USB2_PORT_SHORT(OC_SKIP)"  # TYPE-A Port
 169         register "usb2_ports[6]"  = "USB2_PORT_SHORT(OC_SKIP)"  # TYPE-A Port
 170         register "usb2_ports[7]"  = "USB2_PORT_SHORT(OC_SKIP)"  # mPCIe slot
 171
 172         # USB 3.0 enable ports 1-4, disable ports 5-6
 173         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
 174         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
 175         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
 176         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
 177
 178         register "SerialIoDevMode" = "{ \
 179                 [PchSerialIoIndexI2C0]  = PchSerialIoDisabled, \
 180                 [PchSerialIoIndexI2C1]  = PchSerialIoDisabled, \
 181                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
 182                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
 183                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled, \
 184                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
 185                 [PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
 186                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
 187                 [PchSerialIoIndexUart0] = PchSerialIoDisabled, \
 188                 [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
 189                 [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
 190         }"
 191
 192         device cpu_cluster 0 on
 193                 device lapic 0 on end
 194         end
 195         device domain 0 on
 196                 device pci 00.0 on  end # Host Bridge
 197                 device pci 02.0 on  end # Integrated Graphics Device
 198                 device pci 04.0 off end # SA thermal subsystem
 199                 device pci 05.0 off end # SA IMGU
 200                 device pci 08.0 off end # Gaussian Mixture Model
 201                 device pci 13.0 off end # Integrated Sensor Hub
 202                 device pci 14.0 on  end # USB xHCI
 203                 device pci 14.1 off end # USB xDCI (OTG)
 204                 device pci 14.2 off end # Thermal Subsystem
 205                 device pci 14.3 off end # Camera I/O Host Controller
 206                 device pci 15.0 off end # I2C #0
 207                 device pci 15.1 off end # I2C #1
 208                 device pci 15.2 off end # I2C #2
 209                 device pci 15.3 off end # I2C #3
 210                 device pci 16.0 on  end # Management Engine Interface 1
 211                 device pci 16.1 off end # Management Engine Interface 2
 212                 device pci 16.2 off end # Management Engine IDE-R
 213                 device pci 16.3 off end # Management Engine KT Redirection
 214                 device pci 16.4 off end # Management Engine Interface 3
 215                 device pci 17.0 on  end # SATA
 216                 device pci 19.0 off end # UART #2
 217                 device pci 19.1 off end # I2C #5
 218                 device pci 19.2 off end # I2C #4
 219                 device pci 1c.0 on  end # PCI Express Port 1
 220                 device pci 1c.1 on  end # PCI Express Port 2
 221                 device pci 1c.2 on  end # PCI Express Port 3
 222                 device pci 1c.3 on  end # PCI Express Port 4
 223                 device pci 1c.4 on  end # PCI Express Port 5
 224                 device pci 1c.5 on  end # PCI Express Port 6
 225                 device pci 1c.6 off end # PCI Express Port 7
 226                 device pci 1c.7 off end # PCI Express Port 8
 227                 device pci 1d.0 on      # PCI Express Port 9 - WiFi
 228                         smbios_slot_desc
 229                                 "SlotTypePciExpressMini52pinWithoutBSKO"
 230                                 "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
 231                 end
 232                 device pci 1d.1 off end # PCI Express Port 10
 233                 device pci 1d.2 off end # PCI Express Port 11
 234                 device pci 1d.3 off end # PCI Express Port 12
 235                 device pci 1e.0 off end # UART #0
 236                 device pci 1e.1 off end # UART #1
 237                 device pci 1e.2 off end # GSPI #0
 238                 device pci 1e.3 off end # GSPI #1
 239                 device pci 1e.4 off end # eMMC
 240                 device pci 1e.5 off end # SDIO
 241                 device pci 1e.6 off end # SDCard
 242                 device pci 1f.0 on
 243                         chip superio/ite/it8772f
 244                                 register "peci_tmpin" = "3"
 245                                 register "tmpin1_mode" = "THERMAL_RESISTOR"
 246                                 register "tmpin2_mode" = "THERMAL_RESISTOR"
 247                                 # FAN2 available on fan header but unused
 248                                 device pnp 2e.0 off end # FDC
 249                                 device pnp 2e.1 on # Serial Port 1
 250                                         io 0x60 = 0x3f8
 251                                         irq 0x70 = 4
 252                                 end
 253                                 device pnp 2e.4 on # Environment Controller
 254                                         io 0x60 = 0xa40
 255                                         io 0x62 = 0xa30
 256                                         irq 0x70 = 9
 257                                 end
 258                                 device pnp 2e.5 off end # Keyboard
 259                                 device pnp 2e.6 off end # Mouse
 260                                 device pnp 2e.7 off end # GPIO
 261                                 device pnp 2e.a off end # IR
 262                         end
 263                 end # LPC Interface
 264                 device pci 1f.1 on  end # P2SB
 265                 device pci 1f.2 on  end # Power Management Controller
 266                 device pci 1f.3 off end # Intel HDA
 267                 device pci 1f.4 on  end # SMBus
 268                 device pci 1f.5 off end # PCH SPI
 269                 device pci 1f.6 off end # GbE
 270         end
 271         chip drivers/crb
 272                 device mmio 0xfed40000 on end
 273         end
 274 end