src/mainboard/supermicro/x9scl/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <device/pci_ops.h>
   5 #include <device/pnp_def.h>
   6 #include <device/pnp_ops.h>
   7 #include <bootblock_common.h>
   8 #include <northbridge/intel/sandybridge/sandybridge.h>
   9 #include <northbridge/intel/sandybridge/raminit_native.h>
  10 #include <southbridge/intel/bd82x6x/pch.h>
  11 #include <superio/nuvoton/common/nuvoton.h>
  12 #include <superio/nuvoton/nct6776/nct6776.h>
  13 #include <superio/nuvoton/wpcm450/wpcm450.h>
  14
  15 #include "x9scl.h"
  16
  17 #define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1)
  18 #define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11)
  19
  20 #define SUPERIO_INITVAL(reg, data) {(reg), (data)}
  21 #define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x))
  22
  23 const struct southbridge_usb_port mainboard_usb_ports[] = {
  24         { 1, 0, 0 },    /* ? USB0  1d.0 port 1 */
  25         { 1, 0, 0 },    /* ? USB1  1d.0 port 2 */
  26         { 1, 0, 1 },    /* ? USB2  1d.0 port 3 */
  27         { 1, 0, 1 },    /* ? USB3  1d.0 port 4 */
  28         { 1, 0, 2 },    /* ? USB4  1d.0 port 5 */
  29         { 1, 0, 2 },    /* ? USB5  1d.0 port 6 */
  30         { 1, 0, 3 },    /* ? ???   1a.0 port 1 */
  31         { 1, 0, 3 },    /* ? BMC   1a.0 port 2 */
  32         { 1, 0, 4 },    /* ? ???   1a.0 port 3 */
  33         { 1, 0, 4 },    /* ? USB11 1a.0 port 4 */
  34         { 1, 0, 6 },    /* ? USB12 1a.0 port 5 */
  35         { 1, 0, 5 },    /* ? USB13 1a.0 port 6 */
  36         { 1, 0, 5 },
  37         { 1, 0, 6 },
  38 };
  39
  40 static const uint8_t superio_initvals[][2] = {
  41         /* Global config registers */
  42         SUPERIO_INITVAL(0x1a, 0xc8),
  43         SUPERIO_INITVAL(0x1b, 0x68),
  44         SUPERIO_INITVAL(0x1c, 0x83),
  45         SUPERIO_INITVAL(0x24, 0x24),
  46         SUPERIO_INITVAL(0x2a, 0x00),
  47         SUPERIO_INITVAL(0x2b, 0x42),
  48         SUPERIO_INITVAL(0x2c, 0x80),
  49
  50         SUPERIO_BANK(0x9), /* GPIO[2345] */
  51         SUPERIO_INITVAL(0x30, 0x0c),
  52         SUPERIO_INITVAL(0xe0, 0xcf),
  53         SUPERIO_INITVAL(0xe4, 0xbd),
  54         SUPERIO_INITVAL(0xe5, 0x42),
  55         SUPERIO_INITVAL(0xe9, 0x10),
  56         SUPERIO_INITVAL(0xea, 0x40),
  57         SUPERIO_INITVAL(0xf0, 0xff),
  58         SUPERIO_INITVAL(0xf1, 0x02),
  59
  60         SUPERIO_BANK(0xb), /* HWM & LED */
  61         SUPERIO_INITVAL(0xf7, 0x07),
  62         SUPERIO_INITVAL(0xf8, 0x40),
  63         SUPERIO_INITVAL(0x30, 0x01),
  64         SUPERIO_INITVAL(0x60, X9SCL_NCT6776_HWM_BASE >> 8),
  65         SUPERIO_INITVAL(0x61, X9SCL_NCT6776_HWM_BASE & 0xff),
  66
  67         SUPERIO_BANK(0x5), /* KBC */
  68         SUPERIO_INITVAL(0xf0, 0x83),
  69         SUPERIO_INITVAL(0x30, 0x01),
  70
  71         SUPERIO_BANK(0x0), /* FDC */
  72         SUPERIO_INITVAL(0x30, 0x80),
  73 };
  74
  75 static void superio_init(void)
  76 {
  77         const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0);
  78
  79         nuvoton_pnp_enter_conf_state(dev);
  80         for (size_t i = 0; i < ARRAY_SIZE(superio_initvals); i++)
  81                 pnp_write_config(dev, superio_initvals[i][0], superio_initvals[i][1]);
  82         nuvoton_pnp_exit_conf_state(dev);
  83 }
  84
  85 static void bmc_init(void)
  86 {
  87         pnp_devfn_t dev = KCS_DEV;
  88
  89         pnp_write_config(dev, 0x21, 0x11);
  90
  91         pnp_set_logical_device(dev);
  92         pnp_set_enable(dev, 0);
  93         pnp_set_iobase(dev, PNP_IDX_IO0, X9SCL_WPCM450_KCS_BASE + 0);
  94         pnp_set_iobase(dev, PNP_IDX_IO1, X9SCL_WPCM450_KCS_BASE + 1);
  95         pnp_set_iobase(dev, PNP_IDX_IRQ0, 0);
  96         pnp_set_enable(dev, 1);
  97 }
  98
  99 void bootblock_mainboard_early_init(void)
 100 {
 101         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 102         superio_init();
 103         bmc_init();
 104 }
 105
 106 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 107 {
 108         read_spd(&spd[0], 0x50, id_only);
 109         read_spd(&spd[1], 0x51, id_only);
 110         read_spd(&spd[2], 0x52, id_only);
 111         read_spd(&spd[3], 0x53, id_only);
 112 }
 113
 114 void mainboard_early_init(int s3resume)
 115 {
 116         /* Disable IGD VGA decode, no GTT or GFX stolen */
 117         pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
 118 }