src/mainboard/system76/addw1/devicetree.cb

   1 chip soc/intel/cannonlake
   2         register "common_soc_config" = "{
   3                 // Touchpad I2C bus
   4                 .i2c[0] = {
   5                         .speed = I2C_SPEED_FAST,
   6                         .rise_time_ns = 80,
   7                         .fall_time_ns = 110,
   8                 },
   9         }"
  10
  11 # CPU (soc/intel/cannonlake/cpu.c)
  12         # Power limit
  13         register "power_limits_config" = "{
  14                 .tdp_pl1_override = 45,
  15                 .tdp_pl2_override = 90,
  16         }"
  17
  18         # Enable Enhanced Intel SpeedStep
  19         register "eist_enable" = "1"
  20
  21 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  22         register "enable_c6dram" = "1"
  23
  24 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  25         # Misc
  26         register "AcousticNoiseMitigation" = "1"
  27
  28         # Power
  29         register "PchPmSlpS3MinAssert" = "3" # 50ms
  30         register "PchPmSlpS4MinAssert" = "1" # 1s
  31         register "PchPmSlpSusMinAssert" = "4" # 4s
  32         register "PchPmSlpAMinAssert" = "4" # 2s
  33
  34         # Thermal
  35         register "tcc_offset" = "8"
  36
  37         # Serial IRQ Continuous
  38         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  39
  40 # PM Util (soc/intel/cannonlake/pmutil.c)
  41         # GPE configuration
  42         # Note that GPE events called out in ASL code rely on this
  43         # route. i.e. If this route changes then the affected GPE
  44         # offset bits also need to be changed.
  45         register "gpe0_dw0" = "PMC_GPP_K"
  46         register "gpe0_dw1" = "PMC_GPP_G"
  47         register "gpe0_dw2" = "PMC_GPP_E"
  48
  49 # Actual device tree
  50         device cpu_cluster 0 on
  51                 device lapic 0 on end
  52         end
  53
  54         device domain 0 on
  55                 subsystemid 0x1558 0x65d1 inherit
  56                 device pci 00.0 on  end # Host Bridge
  57                 device pci 01.0 on      # GPU Port
  58                         # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
  59                         register "PcieClkSrcUsage[8]" = "0x40"
  60                         register "PcieClkSrcClkReq[8]" = "8"
  61                 end
  62                 device pci 02.0 on  end # Integrated Graphics Device
  63                 device pci 04.0 on      # SA Thermal device
  64                         register "Device4Enable" = "1"
  65                 end
  66                 device pci 12.0 on  end # Thermal Subsystem
  67                 device pci 12.5 off end # UFS SCS
  68                 device pci 12.6 off end # GSPI #2
  69                 device pci 13.0 off end # Integrated Sensor Hub
  70                 device pci 14.0 on      # USB xHCI
  71                         # USB2
  72                         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
  73                         register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
  74                         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
  75                         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
  76                         register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
  77                         register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
  78                         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
  79                         register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
  80                         register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
  81                         # USB3
  82                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
  83                         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
  84                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
  85                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
  86                         register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
  87                         register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
  88                 end
  89                 device pci 14.2 on  end # Shared SRAM
  90                 device pci 14.3 on      # CNVi wifi
  91                         chip drivers/wifi/generic
  92                                 register "wake" = "PME_B0_EN_BIT"
  93                                 device generic 0 on end
  94                         end
  95                 end
  96                 device pci 14.5 off end # SDCard
  97                 device pci 15.0 on  end # I2C #0
  98                 device pci 15.1 off end # I2C #1
  99                 device pci 15.2 off end # I2C #2
 100                 device pci 15.3 off end # I2C #3
 101                 device pci 16.0 on  end # Management Engine Interface 1
 102                 device pci 16.1 off end # Management Engine Interface 2
 103                 device pci 16.2 off end # Management Engine IDE-R
 104                 device pci 16.3 off end # Management Engine KT Redirection
 105                 device pci 16.4 off end # Management Engine Interface 3
 106                 device pci 16.5 off end # Management Engine Interface 4
 107                 device pci 17.0 on      # SATA
 108                         register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
 109                         register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
 110                 end
 111                 device pci 19.2 off end # UART #2
 112                 device pci 1a.0 off end # eMMC
 113                 device pci 1b.0 on      # PCI Express Port 17
 114                         # PCI Express root port #17 x4, Clock 0 (Thunderbolt)
 115                         register "PcieRpEnable[16]" = "1"
 116                         register "PcieRpLtrEnable[16]" = "1"
 117                         register "PcieRpHotPlug[16]" = "1"
 118                         register "PcieClkSrcUsage[0]" = "16"
 119                         register "PcieClkSrcClkReq[0]" = "0"
 120                 end
 121                 device pci 1b.1 off end # PCI Express Port 18
 122                 device pci 1b.2 off end # PCI Express Port 19
 123                 device pci 1b.3 off end # PCI Express Port 20
 124                 device pci 1b.4 on      # PCI Express Port 21
 125                         # PCI Express root port #21 x4, Clock 10 (SSD2)
 126                         register "PcieRpEnable[20]" = "1"
 127                         register "PcieRpLtrEnable[20]" = "1"
 128                         register "PcieClkSrcUsage[10]" = "20"
 129                         register "PcieClkSrcClkReq[10]" = "10"
 130                         register "PcieRpSlotImplemented[20]" = "1"
 131                 end
 132                 device pci 1b.5 off end # PCI Express Port 22
 133                 device pci 1b.6 off end # PCI Express Port 23
 134                 device pci 1b.7 off end # PCI Express Port 24
 135                 device pci 1c.0 off end # PCI Express Port 1
 136                 device pci 1c.1 off end # PCI Express Port 2
 137                 device pci 1c.2 off end # PCI Express Port 3
 138                 device pci 1c.3 off end # PCI Express Port 4
 139                 device pci 1c.4 off end # PCI Express Port 5
 140                 device pci 1c.5 off end # PCI Express Port 6
 141                 device pci 1c.6 off end # PCI Express Port 7
 142                 device pci 1c.7 off end # PCI Express Port 8
 143                 device pci 1d.0 on      # PCI Express Port 9
 144                         # PCI Express root port #9 x4, Clock 9 (SSD1)
 145                         register "PcieRpEnable[8]" = "1"
 146                         register "PcieRpLtrEnable[8]" = "1"
 147                         register "PcieClkSrcUsage[9]" = "8"
 148                         register "PcieClkSrcClkReq[9]" = "9"
 149                         register "PcieRpSlotImplemented[8]" = "1"
 150                 end
 151                 device pci 1d.1 off end # PCI Express Port 10
 152                 device pci 1d.2 off end # PCI Express Port 11
 153                 device pci 1d.3 off end # PCI Express Port 12
 154                 device pci 1d.4 off end # PCI Express Port 13
 155                 device pci 1d.5 on      # PCI Express Port 14
 156                         # PCI Express root port #14 x1, Clock 5 (GLAN)
 157                         register "PcieRpEnable[13]" = "1"
 158                         register "PcieRpLtrEnable[13]" = "1"
 159                         register "PcieClkSrcUsage[5]" = "13"
 160                         register "PcieClkSrcClkReq[5]" = "5"
 161                         register "PcieRpSlotImplemented[13]" = "1"
 162                 end
 163                 device pci 1d.6 on      # PCI Express Port 15
 164                         # PCI Express root port #15 x1, Clock 7 (Card Reader)
 165                         register "PcieRpEnable[14]" = "1"
 166                         register "PcieRpLtrEnable[14]" = "1"
 167                         register "PcieClkSrcUsage[7]" = "14"
 168                         register "PcieClkSrcClkReq[7]" = "7"
 169                         register "PcieRpSlotImplemented[14]" = "1"
 170                 end
 171                 device pci 1d.7 on      # PCI Express Port 16
 172                         # PCI Express root port #16 x1, Clock 6 (WLAN)
 173                         register "PcieRpEnable[15]" = "1"
 174                         register "PcieRpLtrEnable[15]" = "1"
 175                         register "PcieClkSrcUsage[6]" = "15"
 176                         register "PcieClkSrcClkReq[6]" = "6"
 177                         register "PcieRpSlotImplemented[15]" = "1"
 178                 end
 179                 device pci 1e.0 off end # UART #0
 180                 device pci 1e.1 off end # UART #1
 181                 device pci 1e.2 off end # GSPI #0
 182                 device pci 1e.3 off end # GSPI #1
 183                 device pci 1f.0 on      # LPC Interface
 184                         register "gen1_dec" = "0x00040069"
 185                         register "gen2_dec" = "0x00fc0e01"
 186                         register "gen3_dec" = "0x00fc0f01"
 187                         chip drivers/pc80/tpm
 188                                 device pnp 0c31.0 on end
 189                         end
 190                 end
 191                 device pci 1f.1 off end # P2SB
 192                 device pci 1f.2 hidden end # Power Management Controller
 193                 device pci 1f.3 on      # Intel HDA
 194                         register "PchHdaAudioLinkHda" = "1"
 195                 end
 196                 device pci 1f.4 on      # SMBus
 197                         chip drivers/i2c/tas5825m
 198                                 register "id" = "0"
 199                                 device i2c 4e on end # (8bit address: 0x9c)
 200                         end
 201                 end
 202                 device pci 1f.5 on  end # PCH SPI
 203                 device pci 1f.6 off end # GbE
 204         end
 205 end