src/mainboard/system76/oryp6/devicetree.cb

   1 chip soc/intel/cannonlake
   2         register "common_soc_config" = "{
   3                 // Touchpad I2C bus
   4                 .i2c[0] = {
   5                         .speed = I2C_SPEED_FAST,
   6                         .rise_time_ns = 80,
   7                         .fall_time_ns = 110,
   8                 },
   9         }"
  10
  11 # CPU (soc/intel/cannonlake/cpu.c)
  12         # Power limit
  13         register "power_limits_config" = "{
  14                 .tdp_pl1_override = 45,
  15                 .tdp_pl2_override = 90,
  16         }"
  17
  18         # Enable Enhanced Intel SpeedStep
  19         register "eist_enable" = "1"
  20
  21 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  22         register "enable_c6dram" = "1"
  23
  24 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  25         # Serial I/O
  26         register "SerialIoDevMode" = "{
  27                 [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
  28         }"
  29
  30         # Misc
  31         register "AcousticNoiseMitigation" = "1"
  32
  33         # Power
  34         register "PchPmSlpS3MinAssert" = "3" # 50ms
  35         register "PchPmSlpS4MinAssert" = "1" # 1s
  36         register "PchPmSlpSusMinAssert" = "4" # 4s
  37         register "PchPmSlpAMinAssert" = "4" # 2s
  38
  39         # Thermal
  40         register "tcc_offset" = "8"
  41
  42         # Serial IRQ Continuous
  43         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  44
  45 # PM Util (soc/intel/cannonlake/pmutil.c)
  46         # GPE configuration
  47         # Note that GPE events called out in ASL code rely on this
  48         # route. i.e. If this route changes then the affected GPE
  49         # offset bits also need to be changed.
  50         register "gpe0_dw0" = "PMC_GPP_K"
  51         register "gpe0_dw1" = "PMC_GPP_G"
  52         register "gpe0_dw2" = "PMC_GPP_E"
  53
  54 # Actual device tree
  55         device cpu_cluster 0 on
  56                 device lapic 0 on end
  57         end
  58
  59         device domain 0 on
  60                 device pci 00.0 on  end # Host Bridge
  61                 device pci 01.0 on      # GPU Port
  62                         # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
  63                         register "PcieClkSrcUsage[8]" = "0x40"
  64                         register "PcieClkSrcClkReq[8]" = "8"
  65                 end
  66                 device pci 02.0 on      # Integrated Graphics Device
  67                         register "gfx" = "GMA_DEFAULT_PANEL(0)"
  68                 end
  69                 device pci 04.0 on      # SA Thermal device
  70                         register "Device4Enable" = "1"
  71                 end
  72                 device pci 12.0 on  end # Thermal Subsystem
  73                 device pci 12.5 off end # UFS SCS
  74                 device pci 12.6 off end # GSPI #2
  75                 device pci 13.0 off end # Integrated Sensor Hub
  76                 device pci 14.0 on      # USB xHCI
  77                         # USB2
  78                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
  79                         register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
  80                         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 1
  81                         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 2
  82                         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
  83                         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
  84                         register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
  85                         register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
  86                         # USB3
  87                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
  88                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 1
  89                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 2
  90                 end
  91                 device pci 14.1 off end # USB xDCI (OTG)
  92                 device pci 14.2 on  end # Shared SRAM
  93                 device pci 14.3 on      # CNVi wifi
  94                         chip drivers/wifi/generic
  95                                 register "wake" = "PME_B0_EN_BIT"
  96                                 device generic 0 on end
  97                         end
  98                 end
  99                 device pci 14.5 off end # SDCard
 100                 device pci 15.0 on      # I2C #0
 101                         chip drivers/i2c/hid
 102                                 register "generic.hid" = ""SYNA1202""
 103                                 register "generic.desc" = ""Synaptics Touchpad""
 104                                 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
 105                                 register "generic.detect" = "1"
 106                                 register "hid_desc_reg_offset" = "0x20"
 107                                 device i2c 2c on end
 108                         end
 109                 end
 110                 device pci 15.1 off end # I2C #1
 111                 device pci 15.2 off end # I2C #2
 112                 device pci 15.3 off end # I2C #3
 113                 device pci 16.0 on  end # Management Engine Interface 1
 114                 device pci 16.1 off end # Management Engine Interface 2
 115                 device pci 16.2 off end # Management Engine IDE-R
 116                 device pci 16.3 off end # Management Engine KT Redirection
 117                 device pci 16.4 off end # Management Engine Interface 3
 118                 device pci 16.5 off end # Management Engine Interface 4
 119                 device pci 17.0 on      # SATA
 120                         register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
 121                 end
 122                 device pci 19.0 off end # I2C #4
 123                 device pci 19.1 off end # I2C #5
 124                 device pci 19.2 off end # UART #2
 125                 device pci 1a.0 off end # eMMC
 126                 device pci 1b.0 on      # PCI Express Port 17
 127                         # PCI Express root port #17 x4, Clock 0 (Thunderbolt)
 128                         register "PcieRpEnable[16]" = "1"
 129                         register "PcieRpLtrEnable[16]" = "1"
 130                         register "PcieRpHotPlug[16]" = "1"
 131                         register "PcieClkSrcUsage[0]" = "16"
 132                         register "PcieClkSrcClkReq[0]" = "0"
 133                         register "PcieRpSlotImplemented[16]" = "1"
 134                 end
 135                 device pci 1b.1 off end # PCI Express Port 18
 136                 device pci 1b.2 off end # PCI Express Port 19
 137                 device pci 1b.3 off end # PCI Express Port 20
 138                 device pci 1b.4 on      # PCI Express Port 21
 139                         # PCI Express root port #21 x4, Clock 11 (SSD2)
 140                         register "PcieRpEnable[20]" = "1"
 141                         register "PcieRpLtrEnable[20]" = "1"
 142                         register "PcieClkSrcUsage[11]" = "20"
 143                         register "PcieClkSrcClkReq[11]" = "11"
 144                         register "PcieRpSlotImplemented[20]" = "1"
 145                 end
 146                 device pci 1b.5 off end # PCI Express Port 22
 147                 device pci 1b.6 off end # PCI Express Port 23
 148                 device pci 1b.7 off end # PCI Express Port 24
 149                 device pci 1c.0 off end # PCI Express Port 1
 150                 device pci 1c.1 off end # PCI Express Port 2
 151                 device pci 1c.2 off end # PCI Express Port 3
 152                 device pci 1c.3 off end # PCI Express Port 4
 153                 device pci 1c.4 off end # PCI Express Port 5
 154                 device pci 1c.5 off end # PCI Express Port 6
 155                 device pci 1c.6 off end # PCI Express Port 7
 156                 device pci 1c.7 off end # PCI Express Port 8
 157                 device pci 1d.0 on      # PCI Express Port 9
 158                         # PCI Express root port #9 x4, Clock 12 (SSD1)
 159                         register "PcieRpEnable[8]" = "1"
 160                         register "PcieRpLtrEnable[8]" = "1"
 161                         register "PcieClkSrcUsage[12]" = "8"
 162                         register "PcieClkSrcClkReq[12]" = "12"
 163                         register "PcieRpSlotImplemented[8]" = "1"
 164                 end
 165                 device pci 1d.1 off end # PCI Express Port 10
 166                 device pci 1d.2 off end # PCI Express Port 11
 167                 device pci 1d.3 off end # PCI Express Port 12
 168                 device pci 1d.4 off end # PCI Express Port 13
 169                 device pci 1d.5 on      # PCI Express Port 14
 170                         # PCI Express root port #14 x1, Clock 7 (GLAN)
 171                         register "PcieRpEnable[13]" = "1"
 172                         register "PcieRpLtrEnable[13]" = "1"
 173                         register "PcieClkSrcUsage[7]" = "13"
 174                         register "PcieClkSrcClkReq[7]" = "7"
 175                         register "PcieRpSlotImplemented[13]" = "1"
 176                 end
 177                 device pci 1d.6 on      # PCI Express Port 15
 178                         # PCI Express root port #15 x1, Clock 9 (Card Reader)
 179                         register "PcieRpEnable[14]" = "1"
 180                         register "PcieRpLtrEnable[14]" = "1"
 181                         register "PcieClkSrcUsage[9]" = "14"
 182                         register "PcieClkSrcClkReq[9]" = "9"
 183                         register "PcieRpSlotImplemented[14]" = "1"
 184                 end
 185                 device pci 1d.7 on      # PCI Express Port 16
 186                         # PCI Express root port #16 x1, Clock 6 (WLAN)
 187                         register "PcieRpEnable[15]" = "1"
 188                         register "PcieRpLtrEnable[15]" = "1"
 189                         register "PcieClkSrcUsage[6]" = "15"
 190                         register "PcieClkSrcClkReq[6]" = "6"
 191                         register "PcieRpSlotImplemented[15]" = "1"
 192                 end
 193                 device pci 1e.0 off end # UART #0
 194                 device pci 1e.1 off end # UART #1
 195                 device pci 1e.2 off end # GSPI #0
 196                 device pci 1e.3 off end # GSPI #1
 197                 device pci 1f.0 on      # LPC Interface
 198                         register "gen1_dec" = "0x00040069" # EC PM channel
 199                         register "gen2_dec" = "0x00fc0e01" # AP/EC command
 200                         register "gen3_dec" = "0x00fc0f01" # AP/EC debug
 201                         chip drivers/pc80/tpm
 202                                 device pnp 0c31.0 on end
 203                         end
 204                 end
 205                 device pci 1f.1 off end # P2SB
 206                 device pci 1f.2 hidden end # Power Management Controller
 207                 device pci 1f.3 on      # Intel HDA
 208                         register "PchHdaAudioLinkHda" = "1"
 209                 end
 210                 device pci 1f.4 on      # SMBus
 211                         chip drivers/i2c/tas5825m
 212                                 register "id" = "0"
 213                                 device i2c 4e on end # (8bit address: 0x9c)
 214                         end
 215                 end
 216                 device pci 1f.5 on  end # PCH SPI
 217                 device pci 1f.6 off end # GbE
 218         end
 219 end