src/soc/intel/jasperlake/Kconfig

   1 config SOC_INTEL_JASPERLAKE
   2         bool
   3         help
   4           Intel Jasperlake support
   5
   6 if SOC_INTEL_JASPERLAKE
   7
   8 config CPU_SPECIFIC_OPTIONS
   9         def_bool y
  10         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
  11         select ARCH_X86
  12         select BOOT_DEVICE_SUPPORTS_WRITES
  13         select CACHE_MRC_SETTINGS
  14         select CPU_INTEL_COMMON
  15         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  16         select CPU_SUPPORTS_PM_TIMER_EMULATION
  17         select COS_MAPPED_TO_MSB
  18         select DISPLAY_FSP_VERSION_INFO_2
  19         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  20         select FSP_COMPRESS_FSP_S_LZ4
  21         select FSP_M_XIP
  22         select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
  23         select GENERIC_GPIO_LIB
  24         select HAVE_FSP_GOP
  25         select INTEL_DESCRIPTOR_MODE_CAPABLE
  26         select HAVE_SMI_HANDLER
  27         select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
  28         select IDT_IN_EVERY_STAGE
  29         select INTEL_CAR_NEM_ENHANCED
  30         select INTEL_GMA_ACPI
  31         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  32         select MP_SERVICES_PPI_V1
  33         select MRC_SETTINGS_PROTECT
  34         select PARALLEL_MP_AP_WORK
  35         select PLATFORM_USES_FSP2_2
  36         select PMC_GLOBAL_RESET_ENABLE_LOCK
  37         select SOC_INTEL_COMMON
  38         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  39         select SOC_INTEL_COMMON_BLOCK
  40         select SOC_INTEL_COMMON_BLOCK_ACPI
  41         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  42         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  43         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  44         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  45         select SOC_INTEL_COMMON_BLOCK_CAR
  46         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  47         select SOC_INTEL_COMMON_BLOCK_CNVI
  48         select SOC_INTEL_COMMON_BLOCK_CPU
  49         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  50         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  51         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  52         select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
  53         select SOC_INTEL_COMMON_BLOCK_HDA
  54         select SOC_INTEL_COMMON_BLOCK_SA
  55         select SOC_INTEL_COMMON_BLOCK_SCS
  56         select SOC_INTEL_COMMON_BLOCK_SMM
  57         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  58         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  59         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  60         select SOC_INTEL_COMMON_FSP_RESET
  61         select SOC_INTEL_COMMON_PCH_CLIENT
  62         select SOC_INTEL_COMMON_RESET
  63         select SOC_INTEL_CSE_SET_EOP
  64         select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
  65         select SSE2
  66         select SUPPORT_CPU_UCODE_IN_CBFS
  67         select TSC_MONOTONIC_TIMER
  68         select UDELAY_TSC
  69         select UDK_202005_BINDING
  70         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  71         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  72         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  73         select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
  74
  75 config DCACHE_RAM_BASE
  76         default 0xfef00000
  77
  78 config DCACHE_RAM_SIZE
  79         default 0x80000
  80         help
  81           The size of the cache-as-ram region required during bootblock
  82           and/or romstage.
  83
  84 config DCACHE_BSP_STACK_SIZE
  85         hex
  86         default 0x30400
  87         help
  88           The amount of anticipated stack usage in CAR by bootblock and
  89           other stages. In the case of FSP_USES_CB_STACK default value
  90           will be sum of FSP-M stack requirement(192 KiB) and CB romstage
  91           stack requirement(~1KiB).
  92
  93 config FSP_TEMP_RAM_SIZE
  94         hex
  95         default 0x20000
  96         help
  97           The amount of anticipated heap usage in CAR by FSP.
  98           Refer to Platform FSP integration guide document to know
  99           the exact FSP requirement for Heap setup.
 100
 101 config IFD_CHIPSET
 102         string
 103         default "jsl"
 104
 105 config IED_REGION_SIZE
 106         hex
 107         default 0x400000
 108
 109 config HEAP_SIZE
 110         hex
 111         default 0x8000
 112
 113 config MAX_ROOT_PORTS
 114         int
 115         default 8
 116
 117 config MAX_PCIE_CLOCK_SRC
 118         int
 119         default 6
 120
 121 config SMM_TSEG_SIZE
 122         hex
 123         default 0x800000
 124
 125 config SMM_RESERVED_SIZE
 126         hex
 127         default 0x200000
 128
 129 config PCR_BASE_ADDRESS
 130         hex
 131         default 0xfd000000
 132         help
 133           This option allows you to select MMIO Base Address of sideband bus.
 134
 135 config ECAM_MMCONF_BASE_ADDRESS
 136         default 0xc0000000
 137
 138 config CPU_BCLK_MHZ
 139         int
 140         default 100
 141
 142 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 143         int
 144         default 120
 145
 146 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 147         int
 148         default 133
 149
 150 config CPU_XTAL_HZ
 151         default 38400000
 152
 153 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 154         int
 155         default 3
 156
 157 config SOC_INTEL_I2C_DEV_MAX
 158         int
 159         default 6
 160
 161 config SOC_INTEL_UART_DEV_MAX
 162         int
 163         default 3
 164
 165 config CONSOLE_UART_BASE_ADDRESS
 166         hex
 167         default 0xfe032000
 168         depends on INTEL_LPSS_UART_FOR_CONSOLE
 169
 170 # Clock divider parameters for 115200 baud rate
 171 # Baudrate = (UART source clock * M) /(N *16)
 172 # JSL UART source clock: 100MHz
 173 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 174         hex
 175         default 0x30
 176
 177 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 178         hex
 179         default 0xc35
 180
 181 config VBT_DATA_SIZE_KB
 182         int
 183         default 9
 184
 185 config VBOOT
 186         select VBOOT_MUST_REQUEST_DISPLAY
 187         select VBOOT_STARTS_IN_BOOTBLOCK
 188         select VBOOT_VBNV_CMOS
 189         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 190
 191 config CBFS_SIZE
 192         default 0x200000
 193
 194 config FSP_HEADER_PATH
 195         default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/"
 196
 197 config FSP_FD_PATH
 198         default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
 199
 200 config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT
 201         int "Debug Consent for JSL"
 202         # USB DBC is more common for developers so make this default to 3 if
 203         # SOC_INTEL_DEBUG_CONSENT=y
 204         default 3 if SOC_INTEL_DEBUG_CONSENT
 205         default 0
 206         help
 207           This is to control debug interface on SOC.
 208           Setting non-zero value will allow to use DBC or DCI to debug SOC.
 209           PlatformDebugConsent in FspmUpd.h has the details.
 210
 211           Desired platform debug type are
 212           0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
 213           3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
 214           6:Enable (2-wire DCI OOB), 7:Manual
 215
 216 config PRERAM_CBMEM_CONSOLE_SIZE
 217         hex
 218         default 0x1400
 219 endif