src/soc/intel/tigerlake/lockdown.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Tiger Lake Processor PCH Datasheet
   5  * Document number: 575857
   6  * Chapter number: 4
   7  */
   8
   9 #include <device/mmio.h>
  10 #include <intelblocks/cfg.h>
  11 #include <intelpch/lockdown.h>
  12 #include <soc/pm.h>
  13
  14 static void pmc_lock_pmsync(void)
  15 {
  16         uint8_t *pmcbase;
  17         uint32_t pmsyncreg;
  18
  19         pmcbase = pmc_mmio_regs();
  20
  21         pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
  22         pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
  23         write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
  24 }
  25
  26 static void pmc_lock_abase(void)
  27 {
  28         uint8_t *pmcbase;
  29         uint32_t reg32;
  30
  31         pmcbase = pmc_mmio_regs();
  32
  33         reg32 = read32(pmcbase + GEN_PMCON_B);
  34         reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
  35         write32(pmcbase + GEN_PMCON_B, reg32);
  36 }
  37
  38 static void pmc_lock_smi(void)
  39 {
  40         uint8_t *pmcbase;
  41         uint8_t reg8;
  42
  43         pmcbase = pmc_mmio_regs();
  44
  45         reg8 = read8(pmcbase + GEN_PMCON_B);
  46         reg8 |= SMI_LOCK;
  47         write8(pmcbase + GEN_PMCON_B, reg8);
  48 }
  49
  50 static void pmc_lockdown_cfg(int chipset_lockdown)
  51 {
  52         /* PMSYNC */
  53         pmc_lock_pmsync();
  54         /* Lock down ABASE and sleep stretching policy */
  55         pmc_lock_abase();
  56
  57         if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
  58                 pmc_lock_smi();
  59 }
  60
  61 void soc_lockdown_config(int chipset_lockdown)
  62 {
  63         /* PMC lock down configuration */
  64         pmc_lockdown_cfg(chipset_lockdown);
  65 }