src/superio/fintek/f71808a/f71808a_hwm.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pnp.h>
   6 #include "fintek_internal.h"
   7 #include "chip.h"
   8
   9 /* Intel Ibex Peak/PECI/AMD TSI */
  10 #define HWM_PECI_TSI_CTRL_REG   0x0a
  11 #define HWM_DOMAIN1_EN                  0x0b
  12 #define HWM_TCC_TEMPERATURE_REG 0x0c
  13
  14 /* Fan 1 control */
  15 #define HWM_FAN1_SEG1_SPEED_REG 0xaa
  16 #define HWM_FAN1_SEG2_SPEED_REG 0xab
  17 #define HWM_FAN1_SEG3_SPEED_REG 0xac
  18 #define HWM_FAN1_SEG4_SPEED_REG 0xad
  19 #define HWM_FAN1_SEG5_SPEED_REG 0xae
  20 #define HWM_FAN1_TEMP_SRC_REG   0xaf
  21
  22 #define HWM_FAN1_BOUNDARY_HYSTERESIS    0x98
  23 #define HWM_VT1_BOUNDARY_1_TEMPERATURE  0xa6
  24 #define HWM_VT1_BOUNDARY_2_TEMPERATURE  0xa7
  25 #define HWM_VT1_BOUNDARY_3_TEMPERATURE  0xa8
  26 #define HWM_VT1_BOUNDARY_4_TEMPERATURE  0xa9
  27
  28 /* Fan 2 control */
  29 #define HWM_FAN2_SEG1_SPEED_REG 0xba
  30 #define HWM_FAN2_SEG2_SPEED_REG 0xbb
  31 #define HWM_FAN2_SEG3_SPEED_REG 0xbc
  32 #define HWM_FAN2_SEG4_SPEED_REG 0xbd
  33 #define HWM_FAN2_SEG5_SPEED_REG 0xbe
  34 #define HWM_FAN2_TEMP_SRC_REG   0xbf
  35
  36 void f71808a_hwm_init(struct device *dev)
  37 {
  38         struct resource *res = probe_resource(dev, PNP_IDX_IO0);
  39
  40         if (!res) {
  41                 printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
  42                 return;
  43         }
  44
  45         const struct superio_fintek_f71808a_config *reg = dev->chip_info;
  46         u16 port = res->base;
  47
  48         pnp_enter_conf_mode(dev);
  49
  50         if (reg->hwm_vt1_boundary_1_temperature) {
  51                 pnp_write_index(port, HWM_VT1_BOUNDARY_4_TEMPERATURE,
  52                                 reg->hwm_vt1_boundary_4_temperature);
  53                 pnp_write_index(port, HWM_VT1_BOUNDARY_3_TEMPERATURE,
  54                                 reg->hwm_vt1_boundary_3_temperature);
  55                 pnp_write_index(port, HWM_VT1_BOUNDARY_2_TEMPERATURE,
  56                                 reg->hwm_vt1_boundary_2_temperature);
  57                 pnp_write_index(port, HWM_VT1_BOUNDARY_1_TEMPERATURE,
  58                                 reg->hwm_vt1_boundary_1_temperature);
  59                 pnp_write_index(port, HWM_FAN1_BOUNDARY_HYSTERESIS,
  60                                 reg->hwm_fan1_boundary_hysteresis);
  61                 pnp_write_index(port, HWM_DOMAIN1_EN,
  62                                 reg->hwm_domain1_en);
  63         }
  64
  65         pnp_write_index(port, HWM_PECI_TSI_CTRL_REG, reg->hwm_peci_tsi_ctrl);
  66         pnp_write_index(port, HWM_TCC_TEMPERATURE_REG, reg->hwm_tcc_temp);
  67
  68         pnp_write_index(port, HWM_FAN1_SEG1_SPEED_REG,
  69                                 reg->hwm_fan1_seg1_speed);
  70         pnp_write_index(port, HWM_FAN1_SEG2_SPEED_REG,
  71                                 reg->hwm_fan1_seg2_speed);
  72         pnp_write_index(port, HWM_FAN1_SEG3_SPEED_REG,
  73                                 reg->hwm_fan1_seg3_speed);
  74         pnp_write_index(port, HWM_FAN1_SEG4_SPEED_REG,
  75                                 reg->hwm_fan1_seg4_speed);
  76         pnp_write_index(port, HWM_FAN1_SEG5_SPEED_REG,
  77                                 reg->hwm_fan1_seg5_speed);
  78         pnp_write_index(port, HWM_FAN1_TEMP_SRC_REG, reg->hwm_fan1_temp_src);
  79
  80         pnp_write_index(port, HWM_FAN2_SEG1_SPEED_REG,
  81                                 reg->hwm_fan2_seg1_speed);
  82         pnp_write_index(port, HWM_FAN2_SEG2_SPEED_REG,
  83                                 reg->hwm_fan2_seg2_speed);
  84         pnp_write_index(port, HWM_FAN2_SEG3_SPEED_REG,
  85                                 reg->hwm_fan2_seg3_speed);
  86         pnp_write_index(port, HWM_FAN2_SEG4_SPEED_REG,
  87                                 reg->hwm_fan2_seg4_speed);
  88         pnp_write_index(port, HWM_FAN2_SEG5_SPEED_REG,
  89                                 reg->hwm_fan2_seg5_speed);
  90         pnp_write_index(port, HWM_FAN2_TEMP_SRC_REG, reg->hwm_fan2_temp_src);
  91
  92         pnp_exit_conf_mode(dev);
  93 }