payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / superio / fintek / f81865f / superio.c
blob9181bad98776b06c9ca42e3033152e8c7054f325
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/device.h>
4 #include <device/pnp.h>
5 #include <superio/conf_mode.h>
6 #include <pc80/keyboard.h>
8 #include "f81865f.h"
10 static void f81865f_init(struct device *dev)
13 if (!dev->enabled)
14 return;
16 switch (dev->path.pnp.device) {
17 /* TODO: Might potentially need code for HWM or FDC etc. */
18 case F81865F_KBC:
19 pc_keyboard_init(NO_AUX_DEVICE);
20 break;
24 static struct device_operations ops = {
25 .read_resources = pnp_read_resources,
26 .set_resources = pnp_set_resources,
27 .enable_resources = pnp_enable_resources,
28 .enable = pnp_alt_enable,
29 .init = f81865f_init,
30 .ops_pnp_mode = &pnp_conf_mode_8787_aa,
33 static struct pnp_info pnp_dev_info[] = {
34 /* TODO: Some of the 0x7f8 etc. values may not be correct. */
35 { NULL, F81865F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
36 { NULL, F81865F_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, },
37 { NULL, F81865F_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, },
38 { NULL, F81865F_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
39 { NULL, F81865F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
40 { NULL, F81865F_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, },
41 { NULL, F81865F_GPIO, PNP_IRQ0, },
42 { NULL, F81865F_PME, },
45 static void enable_dev(struct device *dev)
47 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
50 struct chip_operations superio_fintek_f81865f_ops = {
51 CHIP_NAME("Fintek F81865F Super I/O")
52 .enable_dev = enable_dev