payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / superio / smsc / kbc1100 / early_init.c
blob2210c2bf597bb5d6b6a2b8c847e88eb28fde4230
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
5 #include <arch/io.h>
6 #include <device/pnp_ops.h>
7 #include <device/pnp.h>
8 #include <stdint.h>
10 #include "kbc1100.h"
12 static void pnp_enter_conf_state(pnp_devfn_t dev)
14 u16 port = dev >> 8;
15 outb(0x55, port);
18 static void pnp_exit_conf_state(pnp_devfn_t dev)
20 u16 port = dev >> 8;
21 outb(0xaa, port);
24 void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase)
26 pnp_enter_conf_state(dev);
27 pnp_set_logical_device(dev);
28 pnp_set_enable(dev, 0);
29 pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
30 pnp_set_enable(dev, 1);
31 pnp_exit_conf_state(dev);
34 void kbc1100_early_init(u16 port)
36 pnp_devfn_t dev;
37 dev = PNP_DEV(port, KBC1100_KBC);
38 pnp_enter_conf_state(dev);
40 /* Serial IRQ enabled */
41 outb(0x25, port);
42 outb(0x04, port + 1);
44 /* Enable keyboard */
45 pnp_set_logical_device(dev);
46 pnp_set_enable(dev, 0);
47 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
48 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
49 pnp_set_irq(dev, PNP_IDX_IRQ0, 1); /* IRQ 1 */
50 pnp_set_irq(dev, PNP_IDX_IRQ1, 12); /* IRQ 12 */
51 pnp_set_enable(dev, 1);
53 /* Enable EC Channel 0 */
54 dev = PNP_DEV(port, KBC1100_EC0);
55 pnp_set_logical_device(dev);
56 pnp_set_enable(dev, 1);
58 pnp_exit_conf_state(dev);
60 /* disable the 1s timer */
61 outb(0xE7, 0x64);