payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / superio / winbond / w83627dhg / early_serial.c
blob1dcaca08eff2cfcb80047bc665dd3fc018240bbc
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <arch/io.h>
4 #include <device/pnp_ops.h>
5 #include <stdint.h>
6 #include "w83627dhg.h"
8 void pnp_enter_ext_func_mode(pnp_devfn_t dev)
10 u16 port = dev >> 8;
11 outb(0x87, port);
12 outb(0x87, port);
15 void pnp_exit_ext_func_mode(pnp_devfn_t dev)
17 u16 port = dev >> 8;
18 outb(0xaa, port);
21 /**
22 * Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
23 * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or
24 * {RSTOUT3#, RSTOUT2#} or {SDA, SCL}
26 void w83627dhg_enable_i2c(pnp_devfn_t dev)
28 u8 val;
30 pnp_enter_ext_func_mode(dev);
31 pnp_set_logical_device(dev);
33 val = pnp_read_config(dev, 0x2A);
34 val |= 1 << 1;
35 pnp_write_config(dev, 0x2A, val);
37 pnp_exit_ext_func_mode(dev);
40 void w83627dhg_set_clksel_48(pnp_devfn_t dev)
42 u8 reg8;
44 pnp_enter_ext_func_mode(dev);
45 reg8 = pnp_read_config(dev, 0x24);
46 reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
47 pnp_write_config(dev, 0x24, reg8);
48 pnp_exit_ext_func_mode(dev);