src/superio/winbond/w83627dhg/superio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pnp.h>
   5 #include <superio/conf_mode.h>
   6 #include <pc80/keyboard.h>
   7
   8 #include "w83627dhg.h"
   9
  10 static void w83627dhg_enable_UR2(struct device *dev)
  11 {
  12         u8 reg8;
  13
  14         pnp_enter_conf_mode(dev);
  15         reg8 = pnp_read_config(dev, 0x2c);
  16         reg8 |= (0x3);
  17         pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B
  18         pnp_exit_conf_mode(dev);
  19 }
  20
  21 static void w83627dhg_init(struct device *dev)
  22 {
  23
  24         if (!dev->enabled)
  25                 return;
  26
  27         switch (dev->path.pnp.device) {
  28         case W83627DHG_SP2:
  29                 w83627dhg_enable_UR2(dev);
  30                 break;
  31         case W83627DHG_KBC:
  32                 pc_keyboard_init(NO_AUX_DEVICE);
  33                 break;
  34         }
  35 }
  36
  37 static struct device_operations ops = {
  38         .read_resources   = pnp_read_resources,
  39         .set_resources    = pnp_set_resources,
  40         .enable_resources = pnp_enable_resources,
  41         .enable           = pnp_alt_enable,
  42         .init             = w83627dhg_init,
  43         .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
  44 };
  45
  46 static struct pnp_info pnp_dev_info[] = {
  47         { NULL, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
  48         { NULL, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
  49         { NULL, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
  50         { NULL, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
  51         { NULL, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
  52                 0x07ff, 0x07ff, },
  53         { NULL, W83627DHG_SPI, PNP_IO1, 0, 0x7f8, },
  54         { NULL, W83627DHG_GPIO6, },
  55         { NULL, W83627DHG_WDTO_PLED, },
  56         { NULL, W83627DHG_GPIO2, },
  57         { NULL, W83627DHG_GPIO3, },
  58         { NULL, W83627DHG_GPIO4, },
  59         { NULL, W83627DHG_GPIO5, },
  60         { NULL, W83627DHG_ACPI, PNP_IRQ0, },
  61         { NULL, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
  62         { NULL, W83627DHG_PECI_SST, },
  63 };
  64
  65 static void enable_dev(struct device *dev)
  66 {
  67         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
  68 }
  69
  70 struct chip_operations superio_winbond_w83627dhg_ops = {
  71         CHIP_NAME("Winbond W83627DHG Super I/O")
  72         .enable_dev = enable_dev,
  73 };