src/superio/winbond/w83627ehg/superio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pnp.h>
   5 #include <superio/conf_mode.h>
   6 #include <superio/hwm5_conf.h>
   7 #include <console/console.h>
   8 #include <pc80/keyboard.h>
   9 #include <option.h>
  10
  11 #include "w83627ehg.h"
  12
  13 static void enable_hwm_smbus(struct device *dev)
  14 {
  15         u8 reg8;
  16
  17         /* Configure pins 89/90 as SDA/SCL (I2C bus). */
  18         reg8 = pnp_read_config(dev, 0x2a);
  19         reg8 |= (1 << 1);
  20         pnp_write_config(dev, 0x2a, reg8);
  21 }
  22
  23 static void init_acpi(struct device *dev)
  24 {
  25         u8 value;
  26         unsigned int power_on = get_uint_option("power_on_after_fail", 1);
  27
  28         pnp_enter_conf_mode(dev);
  29         pnp_set_logical_device(dev);
  30         value = pnp_read_config(dev, 0xe4);
  31         value &= ~(3 << 5);
  32         if (power_on)
  33                 value |= (1 << 5);
  34         pnp_write_config(dev, 0xe4, value);
  35         pnp_exit_conf_mode(dev);
  36 }
  37
  38 static void init_hwm(u16 base)
  39 {
  40         int i;
  41         u8 reg, value;
  42
  43         /* reg mask data */
  44         u8 hwm_reg_values[] = {
  45                 0x40, 0xff, 0x81, /* Start HWM. */
  46                 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
  47         };
  48
  49         for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
  50                 reg = hwm_reg_values[i];
  51                 value = pnp_read_hwm5_index(base, reg);
  52                 value &= 0xff & (~(hwm_reg_values[i + 1]));
  53                 value |= 0xff & hwm_reg_values[i + 2];
  54                 printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
  55                        "value = 0x%02x\n", base, reg, value);
  56                 pnp_write_hwm5_index(base, reg, value);
  57         }
  58 }
  59
  60 static void w83627ehg_init(struct device *dev)
  61 {
  62         struct resource *res0;
  63
  64         if (!dev->enabled)
  65                 return;
  66
  67         switch (dev->path.pnp.device) {
  68         case W83627EHG_KBC:
  69                 pc_keyboard_init(NO_AUX_DEVICE);
  70                 break;
  71         case W83627EHG_HWM:
  72                 res0 = find_resource(dev, PNP_IDX_IO0);
  73                 init_hwm(res0->base);
  74                 break;
  75         case W83627EHG_ACPI:
  76                 init_acpi(dev);
  77                 break;
  78         }
  79 }
  80
  81 static void w83627ehg_pnp_enable_resources(struct device *dev)
  82 {
  83         pnp_enable_resources(dev);
  84
  85         pnp_enter_conf_mode(dev);
  86         switch (dev->path.pnp.device) {
  87         case W83627EHG_HWM:
  88                 printk(BIOS_DEBUG, "W83627EHG HWM SMBus enabled\n");
  89                 enable_hwm_smbus(dev);
  90                 break;
  91         }
  92         pnp_exit_conf_mode(dev);
  93 }
  94
  95 static struct device_operations ops = {
  96         .read_resources   = pnp_read_resources,
  97         .set_resources    = pnp_set_resources,
  98         .enable_resources = w83627ehg_pnp_enable_resources,
  99         .enable           = pnp_alt_enable,
 100         .init             = w83627ehg_init,
 101         .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
 102 };
 103
 104 static struct pnp_info pnp_dev_info[] = {
 105         { NULL, W83627EHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
 106         { NULL, W83627EHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
 107         { NULL, W83627EHG_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
 108         { NULL, W83627EHG_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
 109         { NULL, W83627EHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
 110                 0x07ff, 0x07ff, },
 111         { NULL, W83627EHG_SFI,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
 112         { NULL, W83627EHG_WDTO_PLED, },
 113         { NULL, W83627EHG_ACPI, PNP_IRQ0, },
 114         { NULL, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, 0x07fe, },
 115
 116         { NULL, W83627EHG_GAME, PNP_IO0, 0x07ff, },
 117         { NULL, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },
 118         { NULL, W83627EHG_GPIO1, },
 119         { NULL, W83627EHG_GPIO2, },
 120         { NULL, W83627EHG_GPIO3, },
 121         { NULL, W83627EHG_GPIO4, },
 122         { NULL, W83627EHG_GPIO5, },
 123         { NULL, W83627EHG_GPIO6, },
 124 };
 125
 126 static void enable_dev(struct device *dev)
 127 {
 128         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 129 }
 130
 131 struct chip_operations superio_winbond_w83627ehg_ops = {
 132         CHIP_NAME("Winbond W83627EHG Super I/O")
 133         .enable_dev = enable_dev,
 134 };