src/superio/winbond/w83627uhg/superio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <device/device.h>
   4 #include <device/pnp.h>
   5 #include <superio/conf_mode.h>
   6 #include <stdint.h>
   7 #include <pc80/keyboard.h>
   8
   9 #include "w83627uhg.h"
  10
  11 /*
  12  * Set the UART clock source.
  13  *
  14  * Possible UART clock source speeds are:
  15  *
  16  *   0 = 1.8462 MHz (default)
  17  *   1 = 2 MHz
  18  *   2 = 24 MHz
  19  *   3 = 14.769 MHz
  20  *
  21  * The faster clocks allow for BAUD rates up to 2mbits.
  22  *
  23  * Warning: The kernel will need to be adjusted since it assumes
  24  * a 1.8462 MHz clock.
  25  */
  26 static void set_uart_clock_source(struct device *dev, u8 uart_clock)
  27 {
  28         u8 value;
  29
  30         pnp_enter_conf_mode(dev);
  31         pnp_set_logical_device(dev);
  32         value = pnp_read_config(dev, PNP_IDX_MSC0);
  33         value &= ~0x03;
  34         value |= (uart_clock & 0x03);
  35         pnp_write_config(dev, PNP_IDX_MSC0, value);
  36         pnp_exit_conf_mode(dev);
  37 }
  38
  39 static void w83627uhg_init(struct device *dev)
  40 {
  41
  42         if (!dev->enabled)
  43                 return;
  44
  45         switch (dev->path.pnp.device) {
  46         case W83627UHG_SP1:
  47                 set_uart_clock_source(dev, 0);
  48                 break;
  49         case W83627UHG_SP2:
  50                 set_uart_clock_source(dev, 0);
  51                 break;
  52         case W83627UHG_SP3:
  53                 set_uart_clock_source(dev, 0);
  54                 break;
  55         case W83627UHG_SP4:
  56                 set_uart_clock_source(dev, 0);
  57                 break;
  58         case W83627UHG_SP5:
  59                 set_uart_clock_source(dev, 0);
  60                 break;
  61         case W83627UHG_SP6:
  62                 set_uart_clock_source(dev, 0);
  63                 break;
  64         case W83627UHG_KBC:
  65                 pc_keyboard_init(NO_AUX_DEVICE);
  66                 break;
  67         }
  68 }
  69
  70 static struct device_operations ops = {
  71         .read_resources   = pnp_read_resources,
  72         .set_resources    = pnp_set_resources,
  73         .enable_resources = pnp_enable_resources,
  74         .enable           = pnp_enable,
  75         .init             = w83627uhg_init,
  76         .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
  77 };
  78
  79 static struct pnp_info pnp_dev_info[] = {
  80         { NULL, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
  81         { NULL, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
  82         { NULL, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
  83         { NULL, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
  84         { NULL, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
  85                 0x07ff, 0x07ff, },
  86         { NULL, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
  87         { NULL, W83627UHG_GPIO3_4, },
  88         { NULL, W83627UHG_WDTO_PLED_GPIO5_6, },
  89         { NULL, W83627UHG_GPIO1_2, },
  90         { NULL, W83627UHG_ACPI, PNP_IRQ0, },
  91         { NULL, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },
  92         { NULL, W83627UHG_PECI_SST, },
  93         { NULL, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
  94         { NULL, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
  95         { NULL, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
  96 };
  97
  98 static void enable_dev(struct device *dev)
  99 {
 100         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 101 }
 102
 103 struct chip_operations superio_winbond_w83627uhg_ops = {
 104         CHIP_NAME("Winbond W83627UHG Super I/O")
 105         .enable_dev = enable_dev,
 106 };