3 This page describes how to run coreboot on the [Elgon] compute board
8 * Add hard reset control
13 +---------------------+------------+
15 +=====================+============+
16 | Socketed flash | no |
17 +---------------------+------------+
19 +---------------------+------------+
21 +---------------------+------------+
22 | In circuit flashing | yes |
23 +---------------------+------------+
25 +---------------------+------------+
26 | Write protection | No |
27 +---------------------+------------+
28 | Dual BIOS feature | No |
29 +---------------------+------------+
30 | Internal flashing | yes |
31 +---------------------+------------+
34 ### Internal programming
36 The SPI flash can be accessed using [flashrom].
38 ### External programming
40 The EVT board does have a pinheader to flash the SOIC-8 in circuit.
41 Directly connecting a Pomona test-clip on the flash is also possible.
43 **Total board view of EVT**
49 **Closeup view of SOIC-8 flash IC and USB serial connector of EVT (marked blue)**
56 **SPI header (marked blue)**
58 ![][elgon_conn_j9_pcb]
60 [elgon_conn_j9_pcb]: elgon_conn_j9_pcb.jpg
64 Dediprog compatible pinout.
68 [elgon_conn_j9]: elgon_conn_j9.png
73 +---------------+----------------------------------------+
74 | SoC | :doc:`../../soc/cavium/cn81xx/index` |
75 +---------------+----------------------------------------+
76 | CPU | Cavium ARMv8-Quadcore `CN81XX`_ |
77 +---------------+----------------------------------------+
79 .. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
82 [Elgon]: https://github.com/Telecominfraproject/OpenCellular
83 [OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
84 [flashrom]: https://flashrom.org/Flashrom