soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / ec / google / chromeec / mux / conn / conn.c
blob1200b5c904de26d119fd2bd0904d4d72a5fb074c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <acpi/acpigen.h>
4 #include <stdio.h>
6 #include "chip.h"
8 static const char *conn_acpi_name(const struct device *dev)
10 static char name[5];
11 snprintf(name, sizeof(name), "CON%1X", dev->path.generic.id);
12 return name;
15 static void conn_fill_ssdt(const struct device *dev)
17 const struct ec_google_chromeec_mux_conn_config *config = dev->chip_info;
18 const char *name;
19 name = acpi_device_name(dev);
20 if (!name)
21 return;
23 acpigen_write_scope(acpi_device_scope(dev));
24 acpigen_write_device(name);
26 acpigen_write_name_integer("_ADR", dev->path.generic.id);
28 if (config) {
29 struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
31 if (config->mode_switch)
32 acpi_dp_add_integer(dsd, "mode-switch", 1);
33 if (config->retimer_switch)
34 acpi_dp_add_integer(dsd, "retimer-switch", 1);
36 acpi_dp_write(dsd);
39 acpigen_write_device_end();
40 acpigen_write_scope_end();
43 static struct device_operations conn_dev_ops = {
44 .read_resources = noop_read_resources,
45 .set_resources = noop_set_resources,
46 .acpi_name = conn_acpi_name,
47 .acpi_fill_ssdt = conn_fill_ssdt,
50 static void conn_enable(struct device *dev)
52 dev->ops = &conn_dev_ops;
55 struct chip_operations ec_google_chromeec_mux_conn_ops = {
56 .name = "CrosEC Type C Mux device",
57 .enable_dev = conn_enable,