src/mainboard/emulation/qemu-q35/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <assert.h>
   6 #include <console/console.h>
   7 #include <cpu/x86/smm.h>
   8 #include <device/pci_ops.h>
   9 #include <mainboard/emulation/qemu-i440fx/memory.h>
  10 #include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
  11 #include <cpu/intel/smm_reloc.h>
  12
  13 #include "q35.h"
  14
  15 static uint32_t encode_pciexbar_length(void)
  16 {
  17         switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
  18         case 256: return 0 << 1;
  19         case 128: return 1 << 1;
  20         case  64: return 2 << 1;
  21         default:  return dead_code_t(uint32_t);
  22         }
  23 }
  24
  25 uint32_t make_pciexbar(void)
  26 {
  27         return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
  28 }
  29
  30 /* Check that MCFG is active. If it's not, QEMU was started for machine PC */
  31 void mainboard_machine_check(void)
  32 {
  33         if (pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) != make_pciexbar())
  34                 die("You must run qemu for machine Q35 (-M q35)");
  35 }
  36
  37 /* Decodes TSEG region size to bytes. */
  38 static size_t decode_tseg_size(u8 esmramc)
  39 {
  40         /* If we intent to enable TSEG, fake it always enabled. */
  41         if (CONFIG(SMM_TSEG))
  42                 esmramc |= T_EN;
  43
  44         if (!(esmramc & T_EN))
  45                 return 0;
  46
  47         switch ((esmramc & TSEG_SZ_MASK) >> 1) {
  48         case 0:
  49                 return 1 * MiB;
  50         case 1:
  51                 return 2 * MiB;
  52         case 2:
  53                 return 8 * MiB;
  54         default:
  55                 return pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB;
  56         }
  57 }
  58
  59 void smm_region(uintptr_t *start, size_t *size)
  60 {
  61         uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
  62
  63         *size = decode_tseg_size(esmramc);
  64         *start = qemu_get_memory_size() * KiB - *size;
  65         printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB);
  66 }
  67
  68 void smm_open(void)
  69 {
  70         /* Set D_OPEN */
  71         if (CONFIG(SMM_ASEG))
  72                 pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG);
  73
  74         if (CONFIG(SMM_TSEG))
  75                 pci_and_config8(HOST_BRIDGE, ESMRAMC, ~T_EN);
  76 }
  77
  78 void smm_close(void)
  79 {
  80         /* Clear D_OPEN */
  81         if (CONFIG(SMM_ASEG))
  82                 pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG);
  83
  84         if (CONFIG(SMM_TSEG))
  85                 pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN);
  86 }
  87
  88 void smm_lock(void)
  89 {
  90         /*
  91          * LOCK the SMM memory window and enable normal SMM.
  92          * After running this function, only a full reset can
  93          * make the SMM registers writable again.
  94          */
  95         printk(BIOS_DEBUG, "Locking SMM.\n");
  96
  97         pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
  98 }