soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / auron / variants / lulu / spd / spd.c
blob33e8c9b55d1463b4597607cc1f81e8d1c66ed9af
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <mainboard/google/auron/variant.h>
4 #include <southbridge/intel/lynxpoint/lp_gpio.h>
6 /* Lulu board memory configuration GPIOs */
7 #define SPD_GPIO_BIT0 13
8 #define SPD_GPIO_BIT1 9
9 #define SPD_GPIO_BIT2 47
10 #define SPD_GPIO_BIT3 8
12 unsigned int variant_get_spd_index(void)
14 const int gpio_vector[] = {
15 SPD_GPIO_BIT0,
16 SPD_GPIO_BIT1,
17 SPD_GPIO_BIT2,
18 SPD_GPIO_BIT3,
19 -1,
21 return get_gpios(gpio_vector);
24 bool variant_is_dual_channel(const unsigned int spd_index)
26 /* CH1 not used in 2GB configurations */
27 return !((spd_index == 0b0000) || (spd_index == 0b0011) || (spd_index == 0b1010));