soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / auron / variants / samus / variant.c
blob441cefe6e8b274ca0e98d40b0910971b1ae9a5d5
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <ec/google/chromeec/ec.h>
5 #include <southbridge/intel/lynxpoint/lp_gpio.h>
6 #include <soc/pm.h>
7 #include <soc/romstage.h>
8 #include <smbios.h>
9 #include <variant/board_version.h>
10 #include <variant/onboard.h>
11 #include <mainboard/google/auron/variant.h>
13 const char *smbios_mainboard_version(void)
15 return samus_board_version();
18 int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
20 /* N/A for SAMUS */
21 return 0;
24 void mainboard_post_raminit(const int s3resume)
26 if (!s3resume)
27 google_chromeec_kbbacklight(100);
29 printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
31 /* Bring SSD out of reset */
32 set_gpio(BOARD_SSD_RESET_GPIO, 1);
35 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
36 * to prevent possible brownout.
38 set_gpio(BOARD_PP3300_AUTOBAHN_GPIO, 1);