soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / brya / smihandler.c
blob2adc62b5a81b8c5aebbe90ea5972cc3d51a2308c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <acpi/acpi.h>
4 #include <cpu/x86/smm.h>
5 #include <ec/google/chromeec/ec.h>
6 #include <ec/google/chromeec/smm.h>
7 #include <elog.h>
8 #include <intelblocks/smihandler.h>
9 #include <intelblocks/xhci.h>
10 #include <variant/ec.h>
12 void mainboard_smi_sleep(u8 slp_typ)
14 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
16 * Workaround: Reset the XHCI controller prior to S5 to avoid
17 * PMC timeout error during poweron from S5.
19 if (slp_typ == ACPI_S5)
20 xhci_host_reset();
23 int mainboard_smi_apmc(u8 apmc)
25 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
26 return 0;
29 void elog_gsmi_cb_mainboard_log_wake_source(void)
31 google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
34 void mainboard_smi_espi_handler(void)
36 chromeec_smi_process_events();