src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

   1 chip soc/intel/alderlake
   2         # As per Intel Advisory doc#723158, the change is required to prevent possible
   3         # display flickering issue.
   4         register "usb2_phy_sus_pg_disable" = "1"
   5
   6         # GPE configuration
   7         register "pmc_gpe0_dw0" = "GPP_A"
   8         register "pmc_gpe0_dw1" = "GPP_E"
   9         register "pmc_gpe0_dw2" = "GPP_F"
  10
  11         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  12         register "gen1_dec" = "0x00fc0801"
  13         register "gen2_dec" = "0x000c0201"
  14         # EC memory map range is 0x900-0x9ff
  15         register "gen3_dec" = "0x00fc0901"
  16
  17         # S0ix enable
  18         register "s0ix_enable" = "true"
  19
  20         # DPTF enable
  21         register "dptf_enable" = "1"
  22
  23         register "tcc_offset" = "10"     # TCC of 90
  24
  25         # Enable CNVi BT
  26         register "cnvi_bt_core" = "true"
  27
  28         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"      # USB2_C0
  29         register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"      # USB2_C1
  30         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"      # USB2_C2
  31         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"     # NFC
  32         register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A Port A3
  33         register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A Port A2
  34         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A Port A1
  35         register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A Port A0
  36         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 Bluetooth
  37
  38         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A0
  39         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI)
  40         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2
  41         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A3
  42
  43         register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
  44         register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
  45         register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
  46
  47         register "serial_io_i2c_mode" = "{
  48                 [PchSerialIoIndexI2C0] = PchSerialIoPci,
  49                 [PchSerialIoIndexI2C1] = PchSerialIoPci,
  50                 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
  51                 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
  52                 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
  53                 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
  54         }"
  55
  56         register "serial_io_gspi_mode" = "{
  57                 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
  58                 [PchSerialIoIndexGSPI1] = PchSerialIoPci,
  59         }"
  60
  61         register "serial_io_uart_mode" = "{
  62                 [PchSerialIoIndexUART0] = PchSerialIoPci,
  63                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
  64                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
  65         }"
  66
  67         register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
  68         register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
  69         register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
  70         register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
  71         register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
  72
  73         # HD Audio
  74         register "pch_hda_dsp_enable" = "1"
  75         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
  76         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
  77         register "pch_hda_idisp_codec_enable" = "1"
  78
  79         # FIVR RFI Spread Spectrum 1.5%
  80         register "fivr_spread_spectrum" = "FIVR_SS_1_5"
  81
  82         # Disable C state auto-demotion for all brask baseboards
  83         register "disable_c1_state_auto_demotion" = "true"
  84
  85         # Intel Common SoC Config
  86         #+-------------------+---------------------------+
  87         #| Field             |  Value                    |
  88         #+-------------------+---------------------------+
  89         #| GSPI1             | Fingerprint MCU           |
  90         #| I2C0              | Audio                     |
  91         #| I2C1              | cr50 TPM. Early init is   |
  92         #|                   | required to set up a BAR  |
  93         #|                   | for TPM communication     |
  94         #+-------------------+---------------------------+
  95         register "common_soc_config" = "{
  96                 .i2c[0] = {
  97                         .speed = I2C_SPEED_FAST,
  98                 },
  99                 .i2c[1] = {
 100                         .early_init = 1,
 101                         .speed = I2C_SPEED_FAST,
 102                         .rise_time_ns = 600,
 103                         .fall_time_ns = 400,
 104                         .data_hold_time_ns = 50,
 105                 },
 106         }"
 107
 108         device domain 0 on
 109                 device ref igpu on end
 110                 device ref dtt on end
 111                 device ref tbt_pcie_rp0 on end
 112                 device ref tbt_pcie_rp1 on end
 113                 device ref tbt_pcie_rp2 on end
 114                 device ref tcss_xhci on end
 115                 device ref tcss_dma0 on end
 116                 device ref tcss_dma1 on end
 117                 device ref xhci on end
 118                 device ref shared_sram on end
 119                 device ref cnvi_wifi on
 120                         chip drivers/wifi/generic
 121                                 register "wake" = "GPE0_PME_B0"
 122                                 register "add_acpi_dma_property" = "true"
 123                                 device generic 0 on end
 124                         end
 125                 end
 126                 device ref i2c1 on
 127                         chip drivers/i2c/tpm
 128                                 register "hid" = ""GOOG0005""
 129                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
 130                                 device i2c 50 on end
 131                         end
 132                 end
 133                 device ref heci1 on end
 134                 device ref sata on end
 135                 device ref pcie_rp7 on
 136                         # Enable PCIE 7 using clk 6
 137                         register "pch_pcie_rp[PCH_RP(7)]" = "{
 138                                 .clk_src = 6,
 139                                 .clk_req = 6,
 140                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
 141                         }"
 142                 end     #PCIE7 RTL8125 Ethernet NIC
 143                 device ref pcie_rp8 on
 144                         # Enable SD Card PCIE 8 using clk 3
 145                         register "pch_pcie_rp[PCH_RP(8)]" = "{
 146                                 .clk_src = 3,
 147                                 .clk_req = 3,
 148                                 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
 149                         }"
 150                 end     #PCIE8 SD card
 151                 device ref uart0 on end
 152                 device ref gspi1 on end
 153                 device ref pch_espi on
 154                         chip ec/google/chromeec
 155                                 device pnp 0c09.0 on end
 156                         end
 157                 end
 158                 device ref hda on end
 159                 device ref smbus on end
 160         end
 161 end