src/mainboard/google/brya/variants/baseboard/brask/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <intelblocks/early_graphics.h>
   6 #include <types.h>
   7 #include <soc/gpio.h>
   8 #include <vendorcode/google/chromeos/chromeos.h>
   9
  10 /* Pad configuration in ramstage */
  11 static const struct pad_config gpio_table[] = {
  12         /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
  13         /* A0  : ESPI_IO0 ==> ESPI_IO_0 */
  14         /* A1  : ESPI_IO1 ==> ESPI_IO_1 */
  15         /* A2  : ESPI_IO2 ==> ESPI_IO_2 */
  16         /* A3  : ESPI_IO3 ==> ESPI_IO_3 */
  17         /* A4  : ESPI_CS# ==> ESPI_CS_L */
  18         /* A5  : ESPI_ALERT0# ==> TP78 */
  19         PAD_NC(GPP_A5, NONE),
  20         /* A6  : ESPI_ALERT1# ==> TP88 */
  21         PAD_NC(GPP_A6, NONE),
  22         /* A7  : SRCCLK_OE7# ==> LAN_WAKE_ODL */
  23         PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE),
  24         /* A8  : SRCCLKREQ7# ==> CLKREQ_7 */
  25         PAD_NC(GPP_A8, NONE),
  26         /* A9  : ESPI_CLK ==> ESPI_CLK */
  27         /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
  28         /* A11 : PMC_I2C_SDA ==> NC */
  29         PAD_NC(GPP_A11, NONE),
  30         /* A12 : SATAXPCIE1 ==> CLKREQ_9B */
  31         PAD_NC(GPP_A12, NONE),
  32         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  33         PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
  34         /* A14 : USB_OC1# ==> USB_C1_OC_ODL */
  35         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  36         /* A15 : USB_OC2# ==> USB_C2_OC_ODL */
  37         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  38         /* A16 : USB_OC3# ==> USB_A0_OC_ODL */
  39         PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG),
  40         /* A17 : DISP_MISCC ==> NC */
  41         PAD_NC(GPP_A17, NONE),
  42         /* A18 : DDSP_HPDB ==> HDMI_HPD */
  43         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  44         /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */
  45         PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6),
  46         /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */
  47         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6),
  48         /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */
  49         PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
  50         /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */
  51         PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
  52         /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
  53         PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
  54
  55         /* B0  : SOC_VID0 */
  56         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  57         /* B1  : SOC_VID1 */
  58         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  59         /* B2  : VRALERT# ==> M2_SSD_PLA_L */
  60         PAD_CFG_GPO(GPP_B2, 1, PLTRST),
  61         /* B3  : PROC_GP2 ==> NC */
  62         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  63         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  64         PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
  65         /* B5  : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */
  66         PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
  67         /* B6  : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */
  68         PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
  69         /* B7  : ISH_12C1_SDA ==> NC */
  70         PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
  71         /* B8  : ISH_I2C1_SCL ==> NC */
  72         PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
  73         /* B9  : NC */
  74         PAD_NC(GPP_B9, NONE),
  75         /* B10 : NC */
  76         PAD_NC(GPP_B10, NONE),
  77         /* B11 : PMCALERT# ==> EN_PP3300_WLAN */
  78         PAD_CFG_GPO(GPP_B11, 1, DEEP),
  79         /* B12 : SLP_S0# ==> SLP_S0_L */
  80         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  81         /* B13 : PLTRST# ==> PLT_RST_L */
  82         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  83         /* B14 : SPKR ==> PWM_PP3300_BUZZER */
  84         PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG),
  85         /* B15 : TIME_SYNC0 ==> TP159 */
  86         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  87         /* B16 : I2C5_SDA ==> NC */
  88         PAD_NC_LOCK(GPP_B16, NONE, LOCK_CONFIG),
  89         /* B17 : I2C5_SCL ==> NC */
  90         PAD_NC_LOCK(GPP_B17, NONE, LOCK_CONFIG),
  91         /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
  92         PAD_NC(GPP_B18, NONE),
  93         /* B19 : NC */
  94         PAD_NC(GPP_B19, NONE),
  95         /* B20 : NC */
  96         PAD_NC(GPP_B20, NONE),
  97         /* B21 : NC */
  98         PAD_NC(GPP_B21, NONE),
  99         /* B22 : NC */
 100         PAD_NC(GPP_B22, NONE),
 101         /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
 102         PAD_NC(GPP_B23, NONE),
 103
 104         /* C0  : SMBCLK ==> DDR_SMB_CLK */
 105         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 106         /* C1  : SMBDATA ==> DDR_SMB_DATA */
 107         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 108         /* C2  : SMBALERT# ==> GPP_C2_STRAP */
 109         PAD_NC(GPP_C2, NONE),
 110         /* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
 111         PAD_NC(GPP_C3, NONE),
 112         /* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
 113         PAD_NC(GPP_C4, NONE),
 114         /* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
 115         PAD_NC(GPP_C5, NONE),
 116         /* C6  : SML1CLK ==> NC */
 117         PAD_NC(GPP_C6, NONE),
 118         /* C7  : SML1DATA ==> NC */
 119         PAD_NC(GPP_C7, NONE),
 120
 121         /* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
 122         PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
 123         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 124         PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
 125         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 126         PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
 127         /* D3  : ISH_GP3 ==> EN_NFC_PWR */
 128         PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG),
 129         /* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
 130         PAD_CFG_GPO(GPP_D4, 1, DEEP),
 131         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
 132         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 133         /* D6  : SRCCLKREQ1# ==> CLKREQ_1 */
 134         PAD_NC(GPP_D6, NONE),
 135         /* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
 136         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 137         /* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
 138         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 139         /* D9  : ISH_SPI_CS# ==> USB_C2_LSX_TX */
 140         PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG),
 141         /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
 142         PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG),
 143         /* D11 : ISH_SPI_MISO ==> DDIA_DP_CTRLCLK */
 144         PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG),
 145         /* D12 : ISH_SPI_MOSI ==> DDIA_DP_CTRLDATA */
 146         PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG),
 147         /* D13 : ISH_UART0_RXD ==> TP97 */
 148         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
 149         /* D14 : ISH_UART0_TXD ==> TP93 */
 150         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
 151         /* D15 : ISH_UART0_RTS# ==> NC */
 152         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
 153         /* D16 : ISH_UART0_CTS# ==> NC */
 154         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 155         /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
 156         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 157         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 158         PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
 159         /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
 160         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 161
 162         /* E0  : SATAXPCIE0 ==> CLKREQ_9 */
 163         PAD_NC(GPP_E0, NONE),
 164         /* E1  : THC0_SPI1_IO2 ==> NC */
 165         PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG),
 166         /* E2  : THC0_SPI1_IO3 ==> NC */
 167         PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG),
 168         /* E3  : PROC_GP0 ==> TP94644 */
 169         PAD_NC(GPP_E3, NONE),
 170         /* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
 171         PAD_CFG_GPO(GPP_E4, 0, DEEP),
 172         /* E5  : SATA_DEVSLP1 ==> NC */
 173         PAD_NC(GPP_E5, NONE),
 174         /* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
 175         PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
 176         /* E7  : PROC_GP1 ==> TP94643 */
 177         PAD_NC(GPP_E7, NONE),
 178         /* E8  : SLP_DRAM# ==> WIFI_DISABLE_L */
 179         PAD_CFG_GPO(GPP_E8, 1, DEEP),
 180         /* E9  : USB_OC0# ==> USB_C0_OC_ODL */
 181         PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
 182         /* E10 : THC0_SPI1_CS# ==> NC */
 183         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 184         /* E11 : THC0_SPI1_CLK ==> NC */
 185         PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 186         /* E12 : THC0_SPI1_IO1 ==> NC */
 187         PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 188         /* E13 : THC0_SPI1_IO2 ==> NC */
 189         PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 190         /* E14 : DDSP_HPDA ==> SOC_DP_HPD */
 191         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 192         /* E15 : RSVD_TP ==> PCH_WP_OD */
 193         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
 194         /* E16 : RSVD_TP ==> CLKREQ_8 */
 195         PAD_NC(GPP_E16, NONE),
 196         /* E17 : THC0_SPI1_INT# ==> TP102 */
 197         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 198         /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_TX */
 199         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
 200         /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_RX_STRAP */
 201         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
 202         /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_TX */
 203         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
 204         /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_RX_STRAP */
 205         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
 206         /* E22 : DDPA_CTRLCLK ==> NC */
 207         PAD_NC(GPP_E22, NONE),
 208         /* E23 : DDPA_CTRLDATA ==> NC */
 209         PAD_NC(GPP_E23, NONE),
 210
 211         /* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
 212         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 213         /* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
 214         PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
 215         /* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
 216         PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
 217         /* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
 218         PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
 219         /* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
 220         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 221         /* F5  : MODEM_CLKREQ ==> CNV_CLKREQ0 */
 222         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
 223         /* F6  : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
 224         PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
 225         /* F7  : GPPF7_STRAP */
 226         PAD_NC(GPP_F7, NONE),
 227         /* F8  : NC */
 228         PAD_NC(GPP_F8, NONE),
 229         /* F9  : BOOTMPC ==> SLP_S0_GATE_R */
 230         PAD_CFG_GPO(GPP_F9, 1, PLTRST),
 231         /* F10 : GPPF10_STRAP */
 232         PAD_NC(GPP_F10, DN_20K),
 233         /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
 234         PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
 235         /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
 236         PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
 237         /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
 238         PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
 239         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 240         PAD_CFG_GPO_LOCK(GPP_F14, 1, LOCK_CONFIG),
 241         /* F15 : GSXSRESET# ==> FPMCU_INT_L */
 242         PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
 243         /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
 244         PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
 245         /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
 246         PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, LEVEL, INVERT),
 247         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 248         PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
 249         /* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */
 250         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 251         /* F20 : EXT_PWR_GATE# ==> TP94669 */
 252         PAD_NC(GPP_F20, NONE),
 253         /* F21 : EXT_PWR_GATE2# ==> TP94579 */
 254         PAD_NC(GPP_F21, NONE),
 255         /* F22 : VNN_CTRL ==> TP153 */
 256         PAD_NC(GPP_F22, NONE),
 257         /* F23 : V1P05_CTRL ==> TP154 */
 258         PAD_NC(GPP_F23, NONE),
 259
 260         /* H0  : GPPH0_BOOT_STRAP1 */
 261         PAD_NC(GPP_H0, NONE),
 262         /* H1  : GPPH1_BOOT_STRAP2 */
 263         PAD_NC(GPP_H1, NONE),
 264         /* H2  : GPPH2_BOOT_STRAP3 */
 265         PAD_NC(GPP_H2, NONE),
 266         /* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
 267         PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG),
 268         /* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
 269         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 270         /* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
 271         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 272         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 273         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
 274         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 275         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
 276         /* H8  : I2C4_SDA ==> WWAN_WLAN_COEX1 */
 277         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
 278         /* H9  : I2C4_SCL ==> WWAN_WLAN_COEX2 */
 279         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
 280         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 281         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 282         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 283         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 284         /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
 285         PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 286         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 287         PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
 288         /* H14 : NC */
 289         PAD_NC(GPP_H14, NONE),
 290         /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
 291         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 292         /* H16 : NC */
 293         PAD_NC(GPP_H16, NONE),
 294         /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
 295         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 296         /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
 297         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 298         /* H19 : SRCCLKREQ4# ==> CLKREQ_4 */
 299         PAD_NC(GPP_H19, NONE),
 300         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 301         PAD_CFG_GPO(GPP_H20, 1, DEEP),
 302         /* H21 : IMGCLKOUT2 ==>  TP94574 */
 303         PAD_NC(GPP_H21, NONE),
 304         /* H22 : IMGCLKOUT3 ==> LAN_PE_ISOLATE_ODL */
 305         PAD_CFG_GPO(GPP_H22, 1, DEEP),
 306         /* H23 : SRCCLKREQ5# ==> M2_SSD_PLN_L */
 307         PAD_CFG_GPO(GPP_H23, 1, PLTRST),
 308
 309         /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
 310         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
 311         /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
 312         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
 313         /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
 314         PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
 315         /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
 316         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 317         /* R4 : HDA_RST# ==> DMIC_CLK0_R */
 318         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 319         /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
 320         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 321         /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
 322         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 323         /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
 324         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 325
 326         /* S0 : SNDW0_CLK ==> NC */
 327         PAD_NC(GPP_S0, NONE),
 328         /* S1 : SNDW0_DATA ==> NC */
 329         PAD_NC(GPP_S1, NONE),
 330         /* S2 : SNDW1_CLK ==> NC */
 331         PAD_NC(GPP_S2, NONE),
 332         /* S3 : SNDW1_DATA ==> NC */
 333         PAD_NC(GPP_S3, NONE),
 334         /* S4 : SNDW2_CLK ==> NC */
 335         PAD_NC(GPP_S4, NONE),
 336         /* S5 : SNDW2_DATA ==> NC */
 337         PAD_NC(GPP_S5, NONE),
 338         /* S6 : SNDW3_CLK ==> NC */
 339         PAD_NC(GPP_S6, NONE),
 340         /* S7 : SNDW3_DATA ==> NC */
 341         PAD_NC(GPP_S7, NONE),
 342
 343         /* GPD0: BATLOW# ==> BATLOW_L */
 344         PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 345         /* GPD1: ACPRESENT ==> ACPRESENT */
 346         PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 347         /* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
 348         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 349         /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
 350         PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 351         /* GPD4: SLP_S3# ==> SLP_S3_L */
 352         PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 353         /* GPD5: SLP_S4# ==> SLP_S4_L */
 354         PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 355         /* GPD6: SLP_A# ==> SLP_A_L_CAP_SITE */
 356         PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 357         /* GPD7: GPD7_STRAP */
 358         PAD_NC(GPD7, NONE),
 359         /* GPD8: SUSCLK ==> PCH_SUSCLK */
 360         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 361         /* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */
 362         PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 363         /* GPD10: SLP_S5# ==> SLP_S5_L */
 364         PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
 365         /* GPD11: LANPHYC ==> TP99 */
 366         PAD_NC(GPD11, NONE),
 367 };
 368
 369 /* Early pad configuration in bootblock */
 370 static const struct pad_config early_gpio_table[] = {
 371         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 372         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 373         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 374         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 375         /*
 376          * D1  : ISH_GP1 ==> FP_RST_ODL
 377          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 378          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 379          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 380          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 381          * FPMCU not working after a S3 resume. This is a known issue.
 382          */
 383         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 384         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 385         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 386         /* E15 : RSVD_TP ==> PCH_WP_OD */
 387         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 388         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 389         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 390         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 391         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 392         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 393         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 394         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 395         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 396         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 397         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 398         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 399         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 400 };
 401
 402 static const struct pad_config romstage_gpio_table[] = {
 403         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 404         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 405 };
 406
 407 const struct pad_config early_graphics_gpio_table[] = {
 408         /* A18 : DDSP_HPDB ==> HDMI_HPD */
 409         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 410         /* D1  : ISH_GP1 ==> HDMI_IN_PLUGIN */
 411         PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
 412         /* D11 : ISH_SPI_MISO ==> HDMIA_CTRLCLK */
 413         PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG),
 414         /* D12 : ISH_SPI_MOSI ==> HDMIA_CTRLDATA */
 415         PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG),
 416         /* E14 : DDSP_HPDA ==> HDMIA_HPD */
 417         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 418         /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
 419         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 420         /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
 421         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 422         /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
 423         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 424         /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
 425         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 426 };
 427
 428 const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
 429 {
 430         *num = ARRAY_SIZE(early_graphics_gpio_table);
 431         return early_graphics_gpio_table;
 432 }
 433
 434 const struct pad_config *__weak variant_gpio_table(size_t *num)
 435 {
 436         *num = ARRAY_SIZE(gpio_table);
 437         return gpio_table;
 438 }
 439
 440 const struct pad_config *__weak variant_gpio_override_table(size_t *num)
 441 {
 442         *num = 0;
 443         return NULL;
 444 }
 445
 446 const struct pad_config *__weak variant_early_gpio_table(size_t *num)
 447 {
 448         *num = ARRAY_SIZE(early_gpio_table);
 449         return early_gpio_table;
 450 }
 451
 452 static const struct cros_gpio cros_gpios[] = {
 453         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 454         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 455 };
 456
 457 DECLARE_WEAK_CROS_GPIOS(cros_gpios);
 458
 459 const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
 460 {
 461         *num = ARRAY_SIZE(romstage_gpio_table);
 462         return romstage_gpio_table;
 463 }