src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb

   1 chip soc/intel/alderlake
   2
   3         # GPE configuration
   4         register "pmc_gpe0_dw0" = "GPP_A"
   5         register "pmc_gpe0_dw1" = "GPP_E"
   6         register "pmc_gpe0_dw2" = "GPP_F"
   7
   8         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
   9         register "gen1_dec" = "0x00fc0801"
  10         register "gen2_dec" = "0x000c0201"
  11         # EC memory map range is 0x900-0x9ff
  12         register "gen3_dec" = "0x00fc0901"
  13
  14         # S0ix enable
  15         register "s0ix_enable" = "true"
  16
  17         # DPTF enable
  18         register "dptf_enable" = "1"
  19
  20         register "tcc_offset" = "10"     # TCC of 90
  21
  22         # Enable CNVi BT
  23         register "cnvi_bt_core" = "true"
  24
  25         register "usb2_ports[0]" = "USB2_PORT_EMPTY"
  26         register "usb2_ports[1]" = "USB2_PORT_EMPTY"
  27         register "usb2_ports[2]" = "USB2_PORT_EMPTY"
  28         register "usb2_ports[3]" = "USB2_PORT_EMPTY"
  29         register "usb2_ports[4]" = "USB2_PORT_EMPTY"
  30         register "usb2_ports[5]" = "USB2_PORT_EMPTY"
  31         register "usb2_ports[6]" = "USB2_PORT_EMPTY"
  32         register "usb2_ports[7]" = "USB2_PORT_EMPTY"
  33         register "usb2_ports[8]" = "USB2_PORT_EMPTY"
  34         register "usb2_ports[9]" = "USB2_PORT_EMPTY"
  35
  36         register "usb3_ports[0]" = "USB3_PORT_EMPTY"
  37         register "usb3_ports[1]" = "USB3_PORT_EMPTY"
  38         register "usb3_ports[2]" = "USB3_PORT_EMPTY"
  39         register "usb3_ports[3]" = "USB3_PORT_EMPTY"
  40
  41         register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
  42         register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
  43         register "tcss_ports[2]" = "TCSS_PORT_EMPTY"
  44         register "tcss_ports[3]" = "TCSS_PORT_EMPTY"
  45
  46         register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
  47         register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
  48         register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
  49         register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
  50         register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
  51
  52         # HD Audio
  53         register "pch_hda_dsp_enable" = "1"
  54         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
  55         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
  56         register "pch_hda_idisp_codec_enable" = "1"
  57
  58         # FIVR RFI Spread Spectrum 1.5%
  59         register "fivr_spread_spectrum" = "FIVR_SS_1_5"
  60
  61         # Disable C state auto-demotion for all brya baseboards
  62         register "disable_c1_state_auto_demotion" = "true"
  63
  64         register "serial_io_uart_mode" = "{
  65                 [PchSerialIoIndexUART0] = PchSerialIoPci,
  66                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
  67                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
  68         }"
  69
  70         device domain 0 on
  71                 # The timing values can be derived from datasheet of display panel
  72                 # You can use EDID string to identify the type of display on the board
  73                 # use below command to get display info from EDID
  74                 # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
  75
  76                 # refer to display PRM document (Volume 2b: Command Reference: Registers)
  77                 # for more info on display control registers
  78                 # https://01.org/linuxgraphics/documentation/hardware-specification-prms
  79                 #+-----------------------------+---------------------------------------+-----+
  80                 #| Intel docs                  | devicetree.cb                         | eDP |
  81                 #+-----------------------------+---------------------------------------+-----+
  82                 #| Power up delay              | `gpu_panel_power_up_delay`            | T3  |
  83                 #+-----------------------------+---------------------------------------+-----+
  84                 #| Power on to backlight on    | `gpu_panel_power_backlight_on_delay`  | T7  |
  85                 #+-----------------------------+---------------------------------------+-----+
  86                 #| Power Down delay            | `gpu_panel_power_down_delay`          | T10 |
  87                 #+-----------------------------+---------------------------------------+-----+
  88                 #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9  |
  89                 #+-----------------------------+---------------------------------------+-----+
  90                 #| Power Cycle Delay           | `gpu_panel_power_cycle_delay`         | T12 |
  91                 #+-----------------------------+---------------------------------------+-----+
  92                 device ref igpu on
  93                         register "panel_cfg" = "{
  94                             .up_delay_ms = 200,
  95                             .down_delay_ms = 50,
  96                             .cycle_delay_ms = 500,
  97                             .backlight_on_delay_ms = 1,
  98                             .backlight_off_delay_ms = 200,
  99                             .backlight_pwm_hz = 200,
 100                         }"
 101                 end
 102                 device ref dtt on end
 103                 device ref tcss_xhci on end
 104                 device ref xhci on end
 105                 device ref shared_sram on end
 106                 device ref cnvi_wifi on
 107                         chip drivers/wifi/generic
 108                                 register "wake" = "GPE0_PME_B0"
 109                                 register "add_acpi_dma_property" = "true"
 110                                 device generic 0 on end
 111                         end
 112                 end
 113                 device ref heci1 on end
 114                 device ref sata on end
 115                 device ref uart0 on end
 116                 device ref pch_espi on
 117                         chip ec/google/chromeec
 118                                 device pnp 0c09.0 on end
 119                         end
 120                 end
 121                 device ref hda on end
 122                 device ref smbus on end
 123         end
 124 end