1 chip soc
/intel
/alderlake
4 register
"pmc_gpe0_dw0" = "GPP_A"
5 register
"pmc_gpe0_dw1" = "GPP_B"
6 register
"pmc_gpe0_dw2" = "GPP_F"
8 # EC host command ranges are in
0x800-0x8ff & 0x200-0x20f
9 register
"gen1_dec" = "0x00fc0801"
10 register
"gen2_dec" = "0x000c0201"
11 # EC memory map range is
0x900-0x9ff
12 register
"gen3_dec" = "0x00fc0901"
14 register
"usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
0
15 register
"usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
1
16 register
"usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
2
17 register
"usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
3
18 register
"usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
4
19 register
"usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
5
20 register
"usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
6
21 register
"usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
7
22 register
"usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
8
23 # USB
2.0 Port #
10 must be used
for integrated BT with Intel CNVi
24 register
"usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port
for CNVi WLAN
25 register
"usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
10
26 register
"usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
11
27 register
"usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
12
28 register
"usb2_ports[13]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
13
29 register
"usb2_ports[14]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
14
30 register
"usb2_ports[15]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port
15
32 register
"usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
0
33 register
"usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
2
34 register
"usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
3
35 register
"usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
4
36 register
"usb3_ports[4]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
5
37 register
"usb3_ports[5]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
6
38 register
"usb3_ports[6]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
7
39 register
"usb3_ports[7]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
8
40 register
"usb3_ports[8]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
9
41 register
"usb3_ports[9]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port
10
43 register
"tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB
-C Port
0
44 register
"tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB
-C Port
1
45 register
"tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB
-C Port
2
46 register
"tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB
-C Port
3
49 register
"pch_hda_sdi_enable[0]" = "true"
50 register
"pch_hda_sdi_enable[1]" = "true"
52 # Vccin Aux Imon Iccmax
, follow RDC#
646929 Power Map requirement
53 register
"vccin_aux_imon_iccmax" = "PD_TIER_VOLUME" #
27A
56 # The timing values can be derived from datasheet of display panel
57 # You can use EDID
string to identify the
type of display on the board
58 # use below command
to get display info from EDID
59 # strings
/sys
/devices
/pci0000
:00/0000:00:02.0/drm
/card0
/card0
-eDP
-1/edid
61 # refer
to display PRM document
(Volume
2b
: Command Reference
: Registers
)
62 #
for more info on display
control registers
63 # https
://01.org
/linuxgraphics
/documentation
/hardware
-specification
-prms
64 #
+-----------------------------+---------------------------------------+-----+
65 #| Intel docs | devicetree.cb | eDP |
66 #
+-----------------------------+---------------------------------------+-----+
67 #| Power up delay | `gpu_panel_power_up_delay` | T3 |
68 #
+-----------------------------+---------------------------------------+-----+
69 #| Power on
to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
70 #
+-----------------------------+---------------------------------------+-----+
71 #| Power Down delay | `gpu_panel_power_down_delay` | T10 |
72 #
+-----------------------------+---------------------------------------+-----+
73 #| Backlight off
to power down | `gpu_panel_power_backlight_off_delay` | T9 |
74 #
+-----------------------------+---------------------------------------+-----+
75 #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
76 #
+-----------------------------+---------------------------------------+-----+
78 register
"panel_cfg" = "{
81 .cycle_delay_ms = 500,
82 .backlight_on_delay_ms = 1,
83 .backlight_off_delay_ms = 200,
84 .backlight_pwm_hz = 200,
88 device ref tcss_xhci on
end
90 chip drivers
/intel
/ish
91 register
"firmware_name" = ""ish_fw.bin
""
92 register
"add_acpi_dma_property" = "true"
93 device generic
0 on
end
96 device ref xhci on
end
97 device ref shared_sram on
end
98 device ref heci1 on
end
99 device ref uart0 on
end
100 device ref pch_espi on
101 chip ec
/google
/chromeec
102 device pnp
0c09.0 on
end