src/mainboard/google/brya/variants/dochi/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A6  : ESPI_ALERT1# ==> NC */
  11         PAD_NC(GPP_A6, NONE),
  12         /* A7  : SRCCLK_OE7# ==> NC */
  13         PAD_NC(GPP_A7, NONE),
  14         /* A8  : SRCCLKREQ7# ==> NC */
  15         PAD_NC(GPP_A8, NONE),
  16         /* A11 : PMC_I2C_SDA ==> NC */
  17         PAD_NC(GPP_A11, NONE),
  18         /* A12 : SATAXPCIE1 ==>  NC  */
  19         PAD_NC(GPP_A12, NONE),
  20         /* A15 : USB_OC2# ==> NC */
  21         PAD_NC(GPP_A15, NONE),
  22         /* A19 : DDSP_HPD1 ==> NC */
  23         PAD_NC(GPP_A19, NONE),
  24         /* A20 : DDSP_HPD2 ==> NC */
  25         PAD_NC(GPP_A20, NONE),
  26
  27         /* B2  : VRALERT# ==> NC */
  28         PAD_NC_LOCK(GPP_B2, NONE, LOCK_CONFIG),
  29         /* B3  : PROC_GP2 ==> NC */
  30         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  31
  32         /* C3 : SML0CLK ==> NC */
  33         PAD_NC_LOCK(GPP_C3, NONE, LOCK_CONFIG),
  34         /* C4 : SML0DATA ==> NC */
  35         PAD_NC_LOCK(GPP_C4, NONE, LOCK_CONFIG),
  36
  37         /* D3  : ISH_GP3 ==> NC */
  38         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  39         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
  40         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
  41         /* D6  : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
  42         PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST),
  43         /* D7  : SRCCLKREQ2# ==> NC */
  44         PAD_NC(GPP_D7, NONE),
  45         /* D8  : SRCCLKREQ3# ==> NC */
  46         PAD_NC(GPP_D8, NONE),
  47         /* D9  : ISH_SPI_CS# ==> NC */
  48         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  49         /* D13 : ISH_UART0_RXD ==> NC */
  50         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  51         /* D14 : ISH_UART0_TXD ==> NC */
  52         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
  53         /* D15 : ISH_UART0_RTS# ==> NC */
  54         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  55         /* D16 : ISH_UART0_CTS# ==> NC */
  56         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  57         /* D17  : UART1_RXD ==> APU_PEN_DETECT_ODL */
  58         PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
  59         /* D18 : UART1_TXD ==> NC */
  60         PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
  61
  62         /* E0  : SATAXPCIE0 ==> NC */
  63         PAD_NC(GPP_E0, NONE),
  64         /* E3  : PROC_GP0 ==> NC */
  65         PAD_NC(GPP_E3, NONE),
  66         /* E4  : SATA_DEVSLP0 ==> NC */
  67         PAD_NC(GPP_E4, NONE),
  68         /* E5  : SATA_DEVSLP1 ==> NC */
  69         PAD_NC(GPP_E5, NONE),
  70         /* E7  : PROC_GP1 ==> NC */
  71         PAD_NC(GPP_E7, NONE),
  72         /* E10 : THC0_SPI1_CS# ==> NC */
  73         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
  74         /* E17 : THC0_SPI1_INT# ==> NC */
  75         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  76         /* E18 : DDP1_CTRLCLK ==> NC */
  77         PAD_NC(GPP_E18, NONE),
  78         /* E20 : DDP2_CTRLCLK ==> NC */
  79         PAD_NC(GPP_E20, NONE),
  80
  81         /* F6  : CNV_PA_BLANKING ==> NC */
  82         PAD_NC(GPP_F6, NONE),
  83         /* F19 : SRCCLKREQ6# ==> NC */
  84         PAD_NC(GPP_F19, NONE),
  85         /* F20 : EXT_PWR_GATE# ==> NC */
  86         PAD_NC(GPP_F20, NONE),
  87         /* F21 : EXT_PWR_GATE2# ==> NC */
  88         PAD_NC(GPP_F21, NONE),
  89
  90         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  91         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
  92         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  93         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
  94         /* H8  : I2C4_SDA ==> NC */
  95         PAD_NC(GPP_H8, NONE),
  96         /* H9  : I2C4_SCL ==> NC */
  97         PAD_NC(GPP_H9, NONE),
  98         /* H12 : I2C7_SDA ==> NC */
  99         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 100         /* H13 : I2C7_SCL ==> NC */
 101         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
 102         /* H19 : SRCCLKREQ4# ==> NC */
 103         PAD_NC(GPP_H19, NONE),
 104         /* H20 : IMGCLKOUT1 ==> NC */
 105         PAD_NC(GPP_H20, NONE),
 106         /* H21 : IMGCLKOUT2 ==> NC */
 107         PAD_NC(GPP_H21, NONE),
 108         /* H22 : IMGCLKOUT3 ==> NC */
 109         PAD_NC(GPP_H22, NONE),
 110         /* H23 : SRCCLKREQ5# ==> NC */
 111         PAD_NC(GPP_H23, NONE),
 112
 113         /* R4 : HDA_RST# ==> DMIC_CLK0_R */
 114         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 115         /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
 116         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 117         /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
 118         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 119         /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
 120         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 121
 122         /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
 123         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 124         /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
 125         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 126         /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
 127         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 128         /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */
 129         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
 130
 131         /* GPD11: LANPHYC ==> NC */
 132         PAD_NC(GPD11, NONE),
 133 };
 134
 135 /* Early pad configuration in bootblock */
 136 static const struct pad_config early_gpio_table[] = {
 137         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 138         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 139         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 140         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 141         /*
 142          * D1  : ISH_GP1 ==> FP_RST_ODL
 143          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 144          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 145          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 146          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 147          * FPMCU not working after a S3 resume. This is a known issue.
 148          */
 149         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 150         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 151         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 152         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 153         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 154         /* E0  : SATAXPCIE0 ==> NC */
 155         PAD_NC(GPP_E0, NONE),
 156         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 157         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 158         /* E15 : RSVD_TP ==> PCH_WP_OD */
 159         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 160         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 161         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 162         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 163         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 164         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 165         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 166         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 167         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 168         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 169         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 170
 171         /* CPU PCIe VGPIO for PEG60 */
 172         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 173         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 174         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 175         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 176         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 177         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 178         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 179         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 180         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 181         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 182         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 183         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 184         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 185         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 186         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 187         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 188         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 189         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 190         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 191         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 192 };
 193
 194 static const struct pad_config romstage_gpio_table[] = {
 195         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 196         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 197
 198         /* Enable touchscreen, hold in reset */
 199         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 200         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 201         /* C1  : SMBDATA ==> USI_RST_L */
 202         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 203
 204         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 205         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 206         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 207         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 208 };
 209
 210 const struct pad_config *variant_gpio_override_table(size_t *num)
 211 {
 212         *num = ARRAY_SIZE(override_gpio_table);
 213         return override_gpio_table;
 214 }
 215
 216 const struct pad_config *variant_early_gpio_table(size_t *num)
 217 {
 218         *num = ARRAY_SIZE(early_gpio_table);
 219         return early_gpio_table;
 220 }
 221
 222 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 223 {
 224         *num = ARRAY_SIZE(romstage_gpio_table);
 225         return romstage_gpio_table;
 226 }