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soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / brya / variants / dochi / overridetree.cb
blobfacdfb2fb3cd54266582386e0b13fff7211a08e0
1 fw_config
2 field FP_MCU 9 10
3 option FP_ABSENT 0
4 option FP_MCU_NUVOTON 1
5 end
6 field STORAGE 30 31
7 option STORAGE_UNKNOWN 0
8 option STORAGE_UFS 1
9 option STORAGE_NVME 2
10 end
11 end
12 chip soc/intel/alderlake
13 register "sagv" = "SaGv_Enabled"
14
15 # As per Intel Advisory doc#723158, the change is required to prevent possible
16 # display flickering issue.
17 register "disable_dynamic_tccold_handshake" = "true"
18
19 # SOC Aux orientation override:
20 # This is a bitfield that corresponds to up to 4 TCSS ports.
21 # Bits (0,1) allocated for TCSS Port1 configuration, Bits (4,5)for TCSS Port3.
22 # TcssAuxOri = 010001b
23 # Bit0,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
24 # Bit1,Bit5 set to "0" indicates Aux lines are not swapped on the
25 # motherboard to USBC connector
26 register "tcss_aux_ori" = "0x11"
27 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
28 register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
29
30 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
31 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3
32 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
33 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
34
35 register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3/2 Type A port3
36 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
37
38 # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
39 # bypass rails implemented.
40 register "ext_fivr_settings" = "{
41 .configure_ext_fivr = 1,
42 }"
43
44 # Enable the Cnvi BT Audio Offload
45 register "cnvi_bt_audio_offload" = "1"
46
47 # Intel Common SoC Config
48 #+-------------------+---------------------------+
49 #| Field | Value |
50 #+-------------------+---------------------------+
51 #| GSPI1 | Fingerprint MCU |
52 #| I2C0 | Audio |
53 #| I2C1 | cr50 TPM. Early init is |
54 #| | required to set up a BAR |
55 #| | for TPM communication |
56 #| I2C3 | TouchScreen |
57 #| I2C5 | Trackpad |
58 #+-------------------+---------------------------+
59 register "common_soc_config" = "{
60 .i2c[0] = {
61 .speed = I2C_SPEED_FAST,
62 },
63 .i2c[1] = {
64 .early_init = 1,
65 .speed = I2C_SPEED_FAST,
66 .rise_time_ns = 550,
67 .fall_time_ns = 400,
68 .data_hold_time_ns = 50,
69 },
70 .i2c[2] = {
71 .speed = I2C_SPEED_FAST,
72 },
73 .i2c[3] = {
74 .speed = I2C_SPEED_FAST,
75 .rise_time_ns = 550,
76 .fall_time_ns = 400,
77 .data_hold_time_ns = 50,
78 },
79 .i2c[5] = {
80 .speed = I2C_SPEED_FAST,
81 },
82 }"
83
84 device domain 0 on
85 device ref tbt_pcie_rp0 off end
86 device ref tbt_pcie_rp1 off end
87 device ref tbt_pcie_rp2 off end
88 device ref tcss_dma0 off end
89 device ref tcss_dma1 off end
90 device ref igpu on
91 chip drivers/gfx/generic
92 register "device_count" = "6"
93 # DDIA for eDP
94 register "device[0].name" = ""LCD0""
95 # Internal panel on the first port of the graphics chip
96 register "device[0].type" = "panel"
97 # DDIB for HDMI
98 register "device[1].name" = ""DD01""
99 # TCP0 (DP-1) for port C0
100 register "device[2].name" = ""DD02""
101 register "device[2].use_pld" = "true"
102 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
103 # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
104 register "device[3].name" = ""DD03""
105 # TCP2 (DP-3) for port C1
106 register "device[4].name" = ""DD04""
107 register "device[4].use_pld" = "true"
108 register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
109 # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
110 register "device[5].name" = ""DD05""
111 device generic 0 on end
112 end
113 end # Integrated Graphics Device
114 device ref dtt on
115 chip drivers/intel/dptf
116 ## sensor information
117 register "options.tsr[0].desc" = ""DRAM""
118 register "options.tsr[1].desc" = ""Soc""
119 register "options.tsr[2].desc" = ""Charger""
120
121 # TODO: below values are initial reference values only
122 ## Active Policy
123 register "policies.active" = "{
124 [0] = {
125 .target = DPTF_CPU,
126 .thresholds = {
127 TEMP_PCT(85, 90),
128 TEMP_PCT(75, 80),
129 TEMP_PCT(68, 70),
130 TEMP_PCT(62, 60),
131 TEMP_PCT(55, 50),
132 TEMP_PCT(50, 40),
133 TEMP_PCT(40, 30),
134 }
135 },
136 [1] = {
137 .target = DPTF_TEMP_SENSOR_1,
138 .thresholds = {
139 TEMP_PCT(60, 90),
140 TEMP_PCT(55, 80),
141 TEMP_PCT(52, 70),
142 TEMP_PCT(48, 60),
143 TEMP_PCT(44, 50),
144 TEMP_PCT(40, 40),
145 TEMP_PCT(36, 30),
146 }
147 }
148 }"
149
150 ## Passive Policy
151 register "policies.passive" = "{
152 [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
153 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
154 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
155 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
156 }"
157
158 ## Critical Policy
159 register "policies.critical" = "{
160 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
161 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
162 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
163 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
164 }"
165
166 register "controls.power_limits" = "{
167 .pl1 = {
168 .min_power = 18000,
169 .max_power = 28000,
170 .time_window_min = 28 * MSECS_PER_SEC,
171 .time_window_max = 32 * MSECS_PER_SEC,
172 .granularity = 200,
173 },
174 .pl2 = {
175 .min_power = 40000,
176 .max_power = 40000,
177 .time_window_min = 28 * MSECS_PER_SEC,
178 .time_window_max = 32 * MSECS_PER_SEC,
179 .granularity = 1000,
180 }
181 }"
182
183 ## Charger Performance Control (Control, mA)
184 register "controls.charger_perf" = "{
185 [0] = { 255, 1700 },
186 [1] = { 24, 1500 },
187 [2] = { 16, 1000 },
188 [3] = { 8, 500 }
189 }"
190
191 ## Fan Performance Control (Percent, Speed, Noise, Power)
192 register "controls.fan_perf" = "{
193 [0] = { 90, 6700, 220, 2200, },
194 [1] = { 80, 5800, 180, 1800, },
195 [2] = { 70, 5000, 145, 1450, },
196 [3] = { 60, 4900, 115, 1150, },
197 [4] = { 50, 3838, 90, 900, },
198 [5] = { 40, 2904, 55, 550, },
199 [6] = { 30, 2337, 30, 300, },
200 [7] = { 20, 1608, 15, 150, },
201 [8] = { 10, 800, 10, 100, },
202 [9] = { 0, 0, 0, 50, }
203 }"
204
205 ## Fan options
206 register "options.fan.fine_grained_control" = "1"
207 register "options.fan.step_size" = "2"
208
209 device generic 0 alias dptf_policy on end
210 end
211 end
212 device ref pcie4_0 on
213 # Enable CPU PCIE RP 1 using CLK 0
214 register "cpu_pcie_rp[CPU_RP(1)]" = "{
215 .clk_req = 0,
216 .clk_src = 0,
217 .flags = PCIE_RP_LTR | PCIE_RP_AER,
218 }"
219 probe STORAGE STORAGE_UNKNOWN
220 probe STORAGE STORAGE_NVME
221 end
222 device ref pcie_rp5 off end
223 device ref pcie_rp6 off end
224 device ref pcie_rp8 off end
225 device ref cnvi_wifi on
226 chip drivers/wifi/generic
227 register "wake" = "GPE0_PME_B0"
228 device generic 0 on end
229 end
230 end
231 device ref i2c0 on
232 chip drivers/i2c/generic
233 register "hid" = ""10EC5650""
234 register "name" = ""RT58""
235 register "desc" = ""Realtek RT5650""
236 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
237 register "property_count" = "1"
238 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
239 register "property_list[0].name" = ""realtek,jd-mode""
240 register "property_list[0].integer" = "2"
241 device i2c 1a on end
242 end
243 end # I2C0
244 device ref i2c1 on
245 chip drivers/i2c/tpm
246 register "hid" = ""GOOG0005""
247 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
248 device i2c 50 on end
249 end
250 end
251 device ref i2c3 on
252 chip drivers/i2c/hid
253 register "generic.hid" = ""ILTK0001""
254 register "generic.desc" = ""ILITEK Touchscreen""
255 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
256 register "generic.detect" = "1"
257 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
258 register "generic.reset_delay_ms" = "200"
259 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
260 register "generic.enable_delay_ms" = "12"
261 register "generic.has_power_resource" = "1"
262 register "hid_desc_reg_offset" = "0x01"
263 device i2c 41 on end
264 end
265 chip drivers/i2c/hid
266 register "generic.hid" = ""ELAN9004""
267 register "generic.desc" = ""ELAN Touchscreen""
268 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
269 register "generic.detect" = "1"
270 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
271 register "generic.reset_delay_ms" = "20"
272 register "generic.reset_off_delay_ms" = "2"
273 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
274 register "generic.enable_delay_ms" = "1"
275 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
276 register "generic.stop_delay_ms" = "150"
277 register "generic.stop_off_delay_ms" = "2"
278 register "generic.has_power_resource" = "1"
279 register "hid_desc_reg_offset" = "0x01"
280 device i2c 10 on end
281 end
282 end
283 device ref i2c5 on
284 chip drivers/i2c/generic
285 register "hid" = ""ELAN0000""
286 register "desc" = ""ELAN Touchpad""
287 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
288 register "wake" = "GPE0_DW2_14"
289 register "detect" = "1"
290 device i2c 15 on end
291 end
292 chip drivers/i2c/hid
293 register "generic.hid" = ""SYNA0000""
294 register "generic.cid" = ""ACPI0C50""
295 register "generic.desc" = ""Synaptics Touchpad""
296 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
297 register "generic.wake" = "GPE0_DW2_14"
298 register "generic.detect" = "1"
299 register "hid_desc_reg_offset" = "0x20"
300 device i2c 0x2c on end
301 end
302 end
303 device ref gspi1 on
304 chip drivers/spi/acpi
305 register "name" = ""CRFP""
306 register "hid" = "ACPI_DT_NAMESPACE_HID"
307 register "uid" = "1"
308 register "compat_string" = ""google,cros-ec-spi""
309 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
310 register "wake" = "GPE0_DW2_15"
311 register "has_power_resource" = "1"
312 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
313 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
314 register "enable_delay_ms" = "3"
315 device spi 0 on
316 probe FP_MCU FP_MCU_NUVOTON
317 end
318 end # FPMCU
319 end
320 device ref pch_espi on
321 chip ec/google/chromeec
322 use conn0 as mux_conn[0]
323 use conn1 as mux_conn[1]
324 device pnp 0c09.0 on end
325 end
326 end
327 device ref ish on
328 chip drivers/intel/ish
329 register "add_acpi_dma_property" = "true"
330 device generic 0 on end
331 end
332 probe STORAGE STORAGE_UNKNOWN
333 probe STORAGE STORAGE_UFS
334 end
335 device ref ufs on
336 probe STORAGE STORAGE_UNKNOWN
337 probe STORAGE STORAGE_UFS
338 end
339 device ref pmc hidden
340 chip drivers/intel/pmc_mux
341 device generic 0 on
342 chip drivers/intel/pmc_mux/conn
343 use usb2_port1 as usb2_port
344 use tcss_usb3_port1 as usb3_port
345 device generic 0 alias conn0 on end
346 end
347 chip drivers/intel/pmc_mux/conn
348 use usb2_port3 as usb2_port
349 use tcss_usb3_port3 as usb3_port
350 device generic 1 alias conn1 on end
351 end
352 end
353 end
354 end
355 device ref tcss_xhci on
356 chip drivers/usb/acpi
357 device ref tcss_root_hub on
358 chip drivers/usb/acpi
359 register "desc" = ""USB3 Type-C Port C0 (MLB)""
360 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
361 register "use_custom_pld" = "true"
362 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
363 device ref tcss_usb3_port1 on end
364 end
365 chip drivers/usb/acpi
366 register "desc" = ""USB3 Type-C Port C1 (MLB)""
367 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
368 register "use_custom_pld" = "true"
369 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
370 register "usb_lpm_incapable" = "true"
371 device ref tcss_usb3_port3 on end
372 end
373 end
374 end
375 end
376 device ref xhci on
377 chip drivers/usb/acpi
378 device ref xhci_root_hub on
379 chip drivers/usb/acpi
380 register "desc" = ""USB2 Type-C Port C0 (MLB)""
381 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
382 register "use_custom_pld" = "true"
383 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
384 device ref usb2_port1 on end
385 end
386 chip drivers/usb/acpi
387 register "desc" = ""USB2 Type-C Port C1 (MLB)""
388 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
389 register "use_custom_pld" = "true"
390 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
391 device ref usb2_port3 on end
392 end
393 chip drivers/usb/acpi
394 register "desc" = ""USB2 Camera""
395 register "type" = "UPC_TYPE_INTERNAL"
396 device ref usb2_port6 on end
397 end
398 chip drivers/usb/acpi
399 register "desc" = ""USB2 Type-A Port A0 (DB)""
400 register "type" = "UPC_TYPE_A"
401 register "use_custom_pld" = "true"
402 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
403 device ref usb2_port9 on end
404 end
405 chip drivers/usb/acpi
406 register "desc" = ""USB2 Bluetooth""
407 register "type" = "UPC_TYPE_INTERNAL"
408 register "reset_gpio" =
409 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
410 device ref usb2_port10 on end
411 end
412 chip drivers/usb/acpi
413 register "desc" = ""USB3 Type-A Port A0 (DB)""
414 register "type" = "UPC_TYPE_USB3_A"
415 register "use_custom_pld" = "true"
416 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
417 device ref usb3_port1 on end
418 end
419 end
420 end
421 end
422 end
423
424 end
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