1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/variants.h>
7 /* Pad configuration in ramstage */
8 static const struct pad_config override_gpio_table
[] = {
9 /* A8 : WWAN_RF_DISABLE_ODL */
10 PAD_CFG_GPO(GPP_A8
, 1, DEEP
),
11 /* H23 : WWAN_SAR_DETECT_ODL */
12 PAD_CFG_GPO(GPP_H23
, 1, DEEP
),
13 /* H3 : WLAN_PCIE_WAKE_ODL */
14 PAD_NC_LOCK(GPP_H3
, NONE
, LOCK_CONFIG
),
15 /* E13 : SRCCLKREQ1# ==> WWAN_EN */
16 PAD_CFG_GPO_LOCK(GPP_E13
, 1, LOCK_CONFIG
),
17 /* F12 : WWAN_RST_L */
18 PAD_CFG_GPO_LOCK(GPP_F12
, 1, LOCK_CONFIG
),
20 /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
21 PAD_CFG_GPO(GPP_A21
, 0, DEEP
),
22 /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
23 PAD_CFG_GPO(GPP_A22
, 1, DEEP
),
25 /* C1 : SMBDATA ==> TCHSCR_RST_L */
26 PAD_CFG_GPO(GPP_C1
, 1, DEEP
),
29 PAD_NC_LOCK(GPP_D3
, NONE
, LOCK_CONFIG
),
30 /* D15 : EN_PP2800_WCAM_X */
31 PAD_NC_LOCK(GPP_D15
, NONE
, LOCK_CONFIG
),
32 /* D16 : EN_PP1800_PP1200_WCAM_X */
33 PAD_NC_LOCK(GPP_D16
, NONE
, LOCK_CONFIG
),
35 /* H19 : SOC_I2C_SUB_INT_ODL */
36 PAD_CFG_GPI_APIC(GPP_H19
, NONE
, PLTRST
, LEVEL
, NONE
),
37 /* H22 : WCAM_MCLK_R */
38 PAD_NC(GPP_H22
, NONE
),
41 /* Early pad configuration in bootblock */
42 static const struct pad_config early_gpio_table
[] = {
43 /* F12 : GSXDOUT ==> WWAN_RST_L */
44 PAD_CFG_GPO(GPP_F12
, 0, DEEP
),
45 /* E13 : SRCCLKREQ1# ==> WWAN_EN */
46 PAD_CFG_GPO(GPP_E13
, 1, DEEP
),
48 /* H12 : UART0_RTS# ==> SD_PERST_L */
49 PAD_CFG_GPO(GPP_H12
, 0, DEEP
),
51 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
52 PAD_CFG_GPO(GPP_H20
, 0, DEEP
),
53 /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
54 PAD_CFG_GPI_APIC(GPP_A13
, NONE
, PLTRST
, LEVEL
, INVERT
),
55 /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
56 PAD_CFG_GPI_GPIO_DRIVER(GPP_E12
, NONE
, DEEP
),
57 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
58 PAD_CFG_GPI(GPP_F18
, NONE
, DEEP
),
59 /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
60 PAD_CFG_NF(GPP_H4
, NONE
, DEEP
, NF1
),
61 /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
62 PAD_CFG_NF(GPP_H5
, NONE
, DEEP
, NF1
),
63 /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
64 PAD_CFG_NF(GPP_H10
, NONE
, DEEP
, NF2
),
65 /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
66 PAD_CFG_NF(GPP_H11
, NONE
, DEEP
, NF2
),
68 /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
69 PAD_CFG_GPO(GPP_H13
, 1, DEEP
),
72 static const struct pad_config romstage_gpio_table
[] = {
73 /* Enable touchscreen, hold in reset */
74 /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
75 PAD_CFG_GPO(GPP_C0
, 1, DEEP
),
76 /* C1 : SMBDATA ==> TCHSCR_RST_L */
77 PAD_CFG_GPO(GPP_C1
, 0, DEEP
),
78 /* H12 : UART0_RTS# ==> SD_PERST_L */
79 PAD_CFG_GPO(GPP_H12
, 1, DEEP
),
80 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
81 PAD_CFG_GPO(GPP_H20
, 1, DEEP
),
84 static const struct pad_config romstage_gpio_table_nontp
[] = {
85 /* H12 : UART0_RTS# ==> SD_PERST_L */
86 PAD_CFG_GPO(GPP_H12
, 1, DEEP
),
87 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
88 PAD_CFG_GPO(GPP_H20
, 1, DEEP
),
91 const struct pad_config
*variant_gpio_override_table(size_t *num
)
93 *num
= ARRAY_SIZE(override_gpio_table
);
94 return override_gpio_table
;
97 const struct pad_config
*variant_early_gpio_table(size_t *num
)
99 *num
= ARRAY_SIZE(early_gpio_table
);
100 return early_gpio_table
;
103 const struct pad_config
*variant_romstage_gpio_table(size_t *num
)
105 if (fw_config_probe(FW_CONFIG(TOUCH_PANEL
, TOUCH_PANEL_DISABLE
))) {
106 *num
= ARRAY_SIZE(romstage_gpio_table_nontp
);
107 return romstage_gpio_table_nontp
;
109 *num
= ARRAY_SIZE(romstage_gpio_table
);
110 return romstage_gpio_table
;