src/mainboard/google/brya/variants/kuldax/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A14 : USB_OC1# ==> HDMIA_HPD */
  11         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2),
  12         /* A15 : USB_OC2# ==> NC */
  13         PAD_NC(GPP_A15, NONE),
  14         /* A19 : DDSP_HPD1 ==> NC */
  15         PAD_NC(GPP_A19, NONE),
  16         /* A20 : DDSP_HPD2 ==> NC */
  17         PAD_NC(GPP_A20, NONE),
  18         /* A21 : DDPC_CTRCLK ==> NC */
  19         PAD_NC(GPP_A21, NONE),
  20         /* A22 : DDPC_CTRLDATA ==> NC */
  21         PAD_NC(GPP_A22, NONE),
  22
  23         /* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
  24         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  25         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
  26         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  27
  28         /* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
  29         PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6),
  30         /* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
  31         PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6),
  32
  33         /* D0  : ISH_GP0 ==> NC */
  34         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  35         /* D1  : ISH_GP1 ==> NC */
  36         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  37         /* D2  : ISH_GP2 ==> NC */
  38         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  39         /* D3  : ISH_GP3 ==> NC */
  40         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  41         /* D9  : ISH_SPI_CS# ==> NC */
  42         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  43
  44         /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
  45         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
  46         /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
  47         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  48
  49         /* F11 : THC1_SPI2_CLK ==> NC */
  50         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  51         /* F12 : GSXDOUT ==> NC */
  52         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  53         /* F13 : GSXDOUT ==> NC */
  54         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  55         /* F15 : GSXSRESET# ==> NC */
  56         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  57         /* F16 : GSXCLK ==> NC */
  58         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
  59
  60         /* R4 : HDA_RST# ==> NC */
  61         PAD_NC(GPP_R4, NONE),
  62         /* R5 : HDA_SDI1 ==> NC */
  63         PAD_NC(GPP_R5, NONE),
  64 };
  65
  66 /* Early pad configuration in bootblock */
  67 static const struct pad_config early_gpio_table[] = {
  68         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  69         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  70         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  71         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  72         /* E15 : RSVD_TP ==> PCH_WP_OD */
  73         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
  74         /* F14 : GSXDIN ==> EN_PP3300_SSD */
  75         PAD_CFG_GPO(GPP_F14, 1, DEEP),
  76         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  77         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  78         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  79         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
  80         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  81         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
  82         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
  83         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  84         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
  85         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  86         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
  87         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  88
  89         /* CPU PCIe VGPIO for PEG60 */
  90         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
  91         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
  92         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
  93         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
  94         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
  95         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
  96         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
  97         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
  98         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
  99         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 100         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 101         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 102         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 103         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 104         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 105         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 106         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 107         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 108         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 109         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 110 };
 111
 112 static const struct pad_config romstage_gpio_table[] = {
 113         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 114         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 115 };
 116
 117 const struct pad_config *variant_gpio_override_table(size_t *num)
 118 {
 119         *num = ARRAY_SIZE(override_gpio_table);
 120         return override_gpio_table;
 121 }
 122
 123 const struct pad_config *variant_early_gpio_table(size_t *num)
 124 {
 125         *num = ARRAY_SIZE(early_gpio_table);
 126         return early_gpio_table;
 127 }
 128
 129 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 130 {
 131         *num = ARRAY_SIZE(romstage_gpio_table);
 132         return romstage_gpio_table;
 133 }