src/mainboard/google/brya/variants/omnigul/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
  11         /* A0  : ESPI_IO0 ==> ESPI_PCH_D0_EC_R */
  12         /* A1  : ESPI_IO1 ==> ESPI_PCH_D1_EC_R */
  13         /* A2  : ESPI_IO2 ==> ESPI_PCH_D2_EC_R */
  14         /* A3  : ESPI_IO3 ==> ESPI_PCH_D3_EC_R */
  15         /* A4  : ESPI_CS# ==> ESPI_PCH_CS_EC_R_L */
  16         /* A5  : ESPI_ALERT0# ==> NC  */
  17         /* A6  : ESPI_ALERT1# ==> NC  */
  18         PAD_NC(GPP_A6, NONE),
  19         /* A7  : SRCCLK_OE7# ==> GPP_A7 */
  20         PAD_CFG_GPI(GPP_A7, NONE, DEEP),
  21         /* A8  : SRCCLKREQ7# ==> NC */
  22         PAD_NC(GPP_A8, NONE),
  23         /* A9  : ESPI_CLK ==> ESPI_PCH_CLK_R */
  24         /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
  25         /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */
  26         /* A12 : SATAXPCIE1 ==> NC */
  27         PAD_NC(GPP_A12, NONE),
  28         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  29         /* A14 : USB_OC1# ==> USB_C1_OC_ODL */
  30         /* A15 : USB_OC2# ==> NC */
  31         PAD_NC(GPP_A15, NONE),
  32         /* A16 : USB_OC3# ==> USB_A0_OC_ODL */
  33         /* A17 : DISP_MISCC ==> EN_FCAM_PWR */
  34         /* A18 : DDSP_HPDB ==> HDMI_HPD */
  35         /* A19 : DDSP_HPD1 ==> NC */
  36         PAD_NC(GPP_A19, NONE),
  37         /* A20 : DDSP_HPD2 ==> NC */
  38         PAD_NC(GPP_A20, NONE),
  39         /* A21 : DDPC_CTRCLK ==> NC */
  40         PAD_NC(GPP_A21, NONE),
  41         /* A22 : DDPC_CTRLDATA ==> NC */
  42         PAD_NC(GPP_A22, NONE),
  43         /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
  44
  45         /* B0  : SOC_VID0 */
  46         /* B1  : SOC_VID1 */
  47         /* B2  : VRALERT# ==> NC */
  48         PAD_NC_LOCK(GPP_B2, NONE, LOCK_CONFIG),
  49         /* B3  : PROC_GP2 ==> GPP_B3 */
  50         PAD_CFG_GPI_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  51         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  52         /* B5  : ISH_I2C0_SDA ==> NC */
  53         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  54         /* B6  : ISH_I2C0_SCL ==> NC */
  55         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  56         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TCHSCR_R_SDA */
  57         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_TCHSCR_R_SCL */
  58         /* B9  : NC */
  59         /* B10 : NC */
  60         /* B11 : PMCALERT# ==> EN_PP3300_WLAN */
  61         /* B12 : SLP_S0# ==> SLP_S0_L */
  62         /* B13 : PLTRST# ==> PLT_RST_L */
  63         /* B14 : SPKR ==> GPP_B14_STRAP */
  64         /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
  65         /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
  66         /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
  67         /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
  68         /* B19 : NC */
  69         /* B20 : NC */
  70         /* B21 : NC */
  71         /* B22 : NC */
  72         /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
  73
  74         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
  75         /* C1  : SMBDATA ==> USI_RST_L */
  76         /* C2  : SMBALERT# ==> GPP_C2_STRAP */
  77         /* C3 : SML0CLK ==> NC */
  78         PAD_NC(GPP_C3, NONE),
  79         /* C4 : SML0DATA ==> NC */
  80         PAD_NC(GPP_C4, NONE),
  81         /* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
  82         /* C6  : SML1CLK ==> USI_REPORT_EN */
  83         /* C7  : SML1DATA ==> USI_INT */
  84
  85         /* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
  86         /* D1  : ISH_GP1 ==> FP_RST_ODL */
  87         /* D2  : ISH_GP2 ==> EN_FP_PWR */
  88         /* D3  : ISH_GP3 ==> NC */
  89         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  90         /* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
  91         /* D5  : SRCCLKREQ0# ==> GPP_D5 */
  92         PAD_CFG_GPI(GPP_D5, NONE, DEEP),
  93         /* D6  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
  94         /* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
  95         /* D8  : SRCCLKREQ3# ==> GPP_D8 */
  96         PAD_CFG_GPI(GPP_D8, NONE, DEEP),
  97         /* D9  : ISH_SPI_CS# ==> NC */
  98         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  99         /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
 100         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
 101         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 102         /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
 103         /* D13 : ISH_UART0_RXD ==> GPP_D13 */
 104         PAD_CFG_GPI_LOCK(GPP_D13, NONE, LOCK_CONFIG),
 105         /* D14 : ISH_UART0_TXD ==> NC */
 106         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
 107         /* D15 : ISH_UART0_RTS# ==> GPP_D15 */
 108         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
 109         /* D16 : ISH_UART0_CTS# ==> GPP_D16 */
 110         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 111         /* D17 : UART1_RXD ==> GPP_D17 */
 112         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 113         /* D18 : UART1_TXD ==> NC */
 114         PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
 115         /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
 116
 117         /* E0  : SATAXPCIE0 ==> NC */
 118         PAD_NC(GPP_E0, NONE),
 119         /* E1  : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
 120         /* E2  : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
 121         /* E3  : PROC_GP0 ==> GPP_E3 */
 122         PAD_CFG_GPI(GPP_E3, NONE, DEEP),
 123         /* E4  : SATA_DEVSLP0 ==> NC */
 124         PAD_NC(GPP_E4, NONE),
 125         /* E5  : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
 126         /* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
 127         /* E7  : PROC_GP1 ==> GPP_E7 */
 128         PAD_CFG_GPI(GPP_E7, NONE, DEEP),
 129         /* E8  : SLP_DRAM# ==> WIFI_DISABLE_L */
 130         /* E9  : USB_OC0# ==> USB_C0_OC_ODL */
 131         /* E10 : THC0_SPI1_CS# ==> GPP_E10 */
 132         PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 133         /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */
 134         /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */
 135         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 136         /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
 137         /* E15 : RSVD_TP ==> PCH_WP_OD */
 138         /* E16 : RSVD_TP ==> NC */
 139         PAD_NC(GPP_E16, NONE),
 140         /* E17 : THC0_SPI1_INT# ==> GPP_E17 */
 141         PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 142         /* E18 : DDP1_CTRLCLK ==> NC */
 143         PAD_NC(GPP_E18, NONE),
 144         /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
 145         PAD_CFG_GPI(GPP_E19, NONE, DEEP),
 146         /* E20 : DDP2_CTRLCLK ==> NC */
 147         PAD_NC(GPP_E20, NONE),
 148         /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
 149         /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_STRAP_P */
 150         /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
 151
 152         /* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
 153         /* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
 154         /* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
 155         /* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
 156         /* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
 157         /* F5  : MODEM_CLKREQ ==> CNV_CLKREQ0 */
 158         /* F6  : CNV_PA_BLANKING ==> NC */
 159         PAD_NC(GPP_F6, NONE),
 160         /* F7  : GPPF7_STRAP */
 161         /* F8  : NC */
 162         /* F9  : BOOTMPC ==> SLP_S0_GATE_R */
 163         /* F10 : GPPF10_STRAP */
 164         /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
 165         /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
 166         /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
 167         /* F14 : GSXDIN ==> TCHPAD_INT_ODL */
 168         /* F15 : GSXSRESET# ==> FPMCU_INT_L */
 169         /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
 170         /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
 171         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 172         /* F19 : SRCCLKREQ6# ==> NC */
 173         PAD_NC(GPP_F19, NONE),
 174         /* F20 : EXT_PWR_GATE# ==> NC */
 175         PAD_NC(GPP_F20, NONE),
 176         /* F21 : EXT_PWR_GATE2# ==> GPP_F21 */
 177         PAD_CFG_GPI(GPP_F21, NONE, DEEP),
 178         /* F22 : NC ==> GPP_F22 */
 179         /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
 180         PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 181
 182         /* H0  : GPPH0_BOOT_STRAP1 */
 183         /* H1  : GPPH1_BOOT_STRAP2 */
 184         /* H2  : GPPH2_BOOT_STRAP3 */
 185         /* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
 186         /* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
 187         /* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
 188         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 189         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 190         /* H8  : I2C4_SDA ==> NC */
 191         PAD_NC(GPP_H8, NONE),
 192         /* H9  : I2C4_SCL ==> NC */
 193         PAD_NC(GPP_H9, NONE),
 194         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 195         /* H11 : UART0_RXD ==> UART_PCH_TX_DBG_RX */
 196         /* H12 : I2C7_SDA ==> GPP_H12 */
 197         PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 198         /* H13 : I2C7_SCL ==> NC */
 199         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
 200         /* H14 : NC */
 201         /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
 202         /* H16 : NC */
 203         /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
 204         /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
 205         /* H19 : SRCCLKREQ4# ==> GPP_H19 */
 206         PAD_CFG_GPI(GPP_H19, NONE, DEEP),
 207         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 208         /* H21 : IMGCLKOUT2 ==>  NC */
 209         PAD_NC(GPP_H21, NONE),
 210         /* H22 : IMGCLKOUT3 ==> NC */
 211         PAD_NC(GPP_H22, NONE),
 212         /* H23 : SRCCLKREQ5# ==> GPP_H23 */
 213         PAD_CFG_GPI(GPP_H23, NONE, DEEP),
 214
 215         /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
 216         /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
 217         /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
 218         /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
 219         /* R4 : HDA_RST# ==> DMIC_CLK1_R */
 220         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 221         /* R5 : HDA_SDI1 ==> DMIC_DATA1_R */
 222         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 223         /* R6 : I2S2_TXD ==> DMIC_CLK0_R */
 224         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 225         /* R7 : I2S2_RXD ==> DMIC_DATA0_R */
 226         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 227
 228         /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
 229         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 230         /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
 231         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 232         /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */
 233         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 234         /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */
 235         PAD_NC(GPP_S3, NONE),
 236         /* S4 : SNDW2_CLK ==> NC */
 237         PAD_NC(GPP_S4, NONE),
 238         /* S5 : SNDW2_DATA ==> NC */
 239         PAD_NC(GPP_S5, NONE),
 240         /* S6 : SNDW3_CLK ==> NC  */
 241         PAD_NC(GPP_S6, NONE),
 242         /* S7 : SNDW3_DATA ==> NC */
 243         PAD_NC(GPP_S7, NONE),
 244
 245         /* GPD0: BATLOW# ==> BATLOW_L */
 246         /* GPD1: ACPRESENT ==> PCH_ACPRESENT */
 247         /* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
 248         /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
 249         /* GPD4: SLP_S3# ==> SLP_S3_R_L */
 250         /* GPD5: SLP_S4# ==> SLP_S4_L */
 251         /* GPD6: SLP_A# ==> SLP_A_L_CAP_SITE */
 252         /* GPD7: GPD7_STRAP */
 253         /* GPD8: SUSCLK ==> PCH_SUSCLK */
 254         /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
 255         /* GPD10: SLP_S5# ==> SLP_S5_L */
 256         /* GPD11: LANPHYC ==> GPD11 */
 257         PAD_NC(GPD11, NONE),
 258
 259         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 260         /* BT_I2S_BCLK */
 261         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
 262         /* BT_I2S_SYNC */
 263         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
 264         /* BT_I2S_SDO */
 265         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
 266         /* BT_I2S_SDI */
 267         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
 268         /* SSP2_SCLK */
 269         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
 270         /* SSP2_SFRM */
 271         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
 272         /* SSP_TXD */
 273         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
 274         /* SSP_RXD */
 275         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
 276 };
 277
 278 /* Early pad configuration in bootblock */
 279 static const struct pad_config early_gpio_table[] = {
 280         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 281         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 282         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 283         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 284         /*
 285          * D1  : ISH_GP1 ==> FP_RST_ODL
 286          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 287          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 288          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 289          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 290          * FPMCU not working after a S3 resume. This is a known issue.
 291          */
 292         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 293         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 294         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 295         /* D11 : SATAXPCIE1 ==> EN_PP3300_SSD */
 296         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 297         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 298         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 299         /* E15 : RSVD_TP ==> PCH_WP_OD */
 300         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
 301         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 302         PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
 303         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 304         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 305         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 306         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 307         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 308         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 309         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 310         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 311 };
 312
 313 static const struct pad_config romstage_gpio_table[] = {
 314         /*
 315          * B4  : PROC_GP3 ==> SSD_PERST_L
 316          * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 317          */
 318         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 319         /* Enable touchscreen, hold in reset */
 320         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 321         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 322         /* C1  : SMBDATA ==> USI_RST_L */
 323         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 324         /* C6  : SML1CLK ==> USI_REPORT_EN */
 325         PAD_CFG_GPO(GPP_C6, 0, DEEP),
 326
 327         // D1  : ISH_GP1 ==> FP_RST_ODL /
 328         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 329         // D2  : ISH_GP2 ==> EN_FP_PWR /
 330         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 331 };
 332
 333 const struct pad_config *variant_gpio_override_table(size_t *num)
 334 {
 335         *num = ARRAY_SIZE(override_gpio_table);
 336         return override_gpio_table;
 337 }
 338
 339 const struct pad_config *variant_early_gpio_table(size_t *num)
 340 {
 341         *num = ARRAY_SIZE(early_gpio_table);
 342         return early_gpio_table;
 343 }
 344
 345 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 346 {
 347         *num = ARRAY_SIZE(romstage_gpio_table);
 348         return romstage_gpio_table;
 349 }