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soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / brya / variants / orisa / overridetree.cb
blobe49714297a9afda70575132f0959dd60a2861951
1 fw_config
2 field THERMAL_SOLUTION 0 0
3 option THERMAL_SOLUTION_6W 0
4 option THERMAL_SOLUTION_15W 1
5 end
6 field PDC_CONTROL 1 2
7 option PDC_CONTROL_UNKNOWN 0
8 option PDC_RTS_BYPASS 1
9 option PDC_TI_BYPASS 2
10 end
11 field STORAGE 30 31
12 option STORAGE_EMMC 0
13 option STORAGE_NVME 1
14 option STORAGE_UFS 2
15 option STORAGE_UNKNOWN 3
16 end
17 end
18
19 chip soc/intel/alderlake
20 register "sagv" = "SaGv_Enabled"
21
22 # S0ix enable
23 register "s0ix_enable" = "true"
24
25 # DPTF enable
26 register "dptf_enable" = "1"
27
28 register "tcc_offset" = "10" # TCC of 90
29
30 # Enable CNVi BT
31 register "cnvi_bt_core" = "true"
32
33 # eMMC HS400
34 register "emmc_enable_hs400_mode" = "true"
35
36 #eMMC DLL tuning parameters
37 # EMMC Tx CMD Delay
38 # Refer to EDS-Vol2-42.3.7.
39 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
40 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
41 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
42
43 # EMMC TX DATA Delay 1
44 # Refer to EDS-Vol2-42.3.8.
45 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
46 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
47 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
48
49 # EMMC TX DATA Delay 2
50 # Refer to EDS-Vol2-42.3.9.
51 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
52 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
53 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
54 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
55 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
56
57 # EMMC RX CMD/DATA Delay 1
58 # Refer to EDS-Vol2-42.3.10.
59 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
60 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
61 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
62 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
63 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
64
65 # EMMC RX CMD/DATA Delay 2
66 # Refer to EDS-Vol2-42.3.12.
67 # [17:16] stands for Rx Clock before Output Buffer,
68 # 00: Rx clock after output buffer,
69 # 01: Rx clock before output buffer,
70 # 10: Automatic selection based on working mode.
71 # 11: Reserved
72 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
73 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
74 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
75
76 # EMMC Rx Strobe Delay
77 # Refer to EDS-Vol2-42.3.11.
78 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
79 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
80 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
81
82 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
83 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
84 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
85 register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
86
87 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
88 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
89
90 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
91
92 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
93 # Bit 2 - C1 has a redriver which does SBU muxing.
94 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
95 register "tcss_aux_ori" = "0"
96
97 # HD Audio
98 register "pch_hda_dsp_enable" = "1"
99 register "pch_hda_audio_link_hda_enable" = "1"
100 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
101 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
102 register "pch_hda_idisp_codec_enable" = "1"
103
104 # Configure external V1P05/Vnn/VnnSx Rails
105 register "ext_fivr_settings" = "{
106 .configure_ext_fivr = 1,
107 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
108 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
109 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
110 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
111 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
112 .v1p05_voltage_mv = 1050,
113 .vnn_voltage_mv = 780,
114 .vnn_sx_voltage_mv = 1050,
115 .v1p05_icc_max_ma = 500,
116 .vnn_icc_max_ma = 500,
117 }"
118
119 register "serial_io_i2c_mode" = "{
120 [PchSerialIoIndexI2C0] = PchSerialIoPci,
121 [PchSerialIoIndexI2C1] = PchSerialIoPci,
122 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
123 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
124 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
125 [PchSerialIoIndexI2C5] = PchSerialIoPci,
126 }"
127
128 register "serial_io_gspi_mode" = "{
129 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
130 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
131 }"
132
133 register "serial_io_uart_mode" = "{
134 [PchSerialIoIndexUART0] = PchSerialIoPci,
135 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
136 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
137 }"
138
139 # FIXME: To be enabled in future based on PNP impact data.
140 # Disable Package C-state demotion for nissa baseboard.
141 register "disable_package_c_state_demotion" = "true"
142
143 # Intel Common SoC Config
144 #+-------------------+---------------------------+
145 #| Field | Value |
146 #+-------------------+---------------------------+
147 #| I2C0 | TPM. Early init is |
148 #| | required to set up a BAR |
149 #| | for TPM communication |
150 #| I2C1 | Trackpad |
151 #| I2C5 | Touchscreen |
152 #+-------------------+---------------------------+
153 register "common_soc_config" = "{
154 .i2c[0] = {
155 .early_init = 1,
156 .speed = I2C_SPEED_FAST_PLUS,
157 .speed_config[0] = {
158 .speed = I2C_SPEED_FAST_PLUS,
159 .scl_lcnt = 55,
160 .scl_hcnt = 30,
161 .sda_hold = 7,
162 }
163 },
164 .i2c[1] = {
165 .speed = I2C_SPEED_FAST,
166 .speed_config[0] = {
167 .speed = I2C_SPEED_FAST,
168 .scl_lcnt = 158,
169 .scl_hcnt = 79,
170 .sda_hold = 7,
171 }
172 },
173 .i2c[5] = {
174 .speed = I2C_SPEED_FAST,
175 .speed_config[0] = {
176 .speed = I2C_SPEED_FAST,
177 .scl_lcnt = 158,
178 .scl_hcnt = 79,
179 .sda_hold = 7,
180 }
181 },
182 }"
183
184 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
185 .tdp_pl1_override = 20,
186 .tdp_pl2_override = 25,
187 .tdp_pl4 = 78,
188 }"
189
190 register "power_limits_config[ADL_N_081_15W_CORE]" = "{
191 .tdp_pl1_override = 20,
192 .tdp_pl2_override = 35,
193 .tdp_pl4 = 83,
194 }"
195
196 device domain 0 on
197 device ref igpu on end
198 device ref dtt on
199 chip drivers/intel/dptf
200 ## sensor information
201 register "options.tsr[0].desc" = ""DDR""
202 register "options.tsr[1].desc" = ""charger""
203 register "options.tsr[2].desc" = ""ambient""
204
205 ## Active Policy
206 register "policies.active" = "{
207 [0] = {
208 .target = DPTF_CPU,
209 .thresholds = {
210 TEMP_PCT(70, 100),
211 TEMP_PCT(60, 65),
212 TEMP_PCT(42, 60),
213 TEMP_PCT(39, 55),
214 TEMP_PCT(38, 50),
215 TEMP_PCT(35, 43),
216 TEMP_PCT(31, 30),
217 }
218 },
219 [1] = {
220 .target = DPTF_TEMP_SENSOR_0,
221 .thresholds = {
222 TEMP_PCT(60, 100),
223 TEMP_PCT(55, 65),
224 TEMP_PCT(52, 60),
225 TEMP_PCT(50, 55),
226 TEMP_PCT(48, 50),
227 TEMP_PCT(45, 43),
228 TEMP_PCT(41, 30),
229 }
230 }
231 }"
232
233 ## Passive Policy
234 register "policies.passive" = "{
235 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
236 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
237 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
238 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
239 }"
240
241 ## Critical Policy
242 register "policies.critical" = "{
243 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
244 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
245 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
246 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
247 }"
248
249 register "controls.power_limits" = "{
250 .pl1 = {
251 .min_power = 6000,
252 .max_power = 20000,
253 .time_window_min = 28 * MSECS_PER_SEC,
254 .time_window_max = 28 * MSECS_PER_SEC,
255 .granularity = 500
256 },
257 .pl2 = {
258 .min_power = 25000,
259 .max_power = 25000,
260 .time_window_min = 32 * MSECS_PER_SEC,
261 .time_window_max = 32 * MSECS_PER_SEC,
262 .granularity = 500
263 }
264 }"
265
266 ## Charger Performance Control (Control, mA)
267 register "controls.charger_perf" = "{
268 [0] = { 255, 1700 },
269 [1] = { 24, 1500 },
270 [2] = { 16, 1000 },
271 [3] = { 8, 500 }
272 }"
273
274 ## Fan Performance Control (Percent, Speed, Noise, Power)
275 register "controls.fan_perf" = "{
276 [0] = { 100, 6000, 220, 2200, },
277 [1] = { 92, 5500, 180, 1800, },
278 [2] = { 85, 5000, 145, 1450, },
279 [3] = { 70, 4400, 115, 1150, },
280 [4] = { 56, 3900, 90, 900, },
281 [5] = { 45, 3300, 55, 550, },
282 [6] = { 38, 3000, 30, 300, },
283 [7] = { 33, 2900, 15, 150, },
284 [8] = { 10, 800, 10, 100, },
285 [9] = { 0, 0, 0, 50, }
286 }"
287
288 ## Fan options
289 register "options.fan.fine_grained_control" = "1"
290 register "options.fan.step_size" = "2"
291
292 device generic 0 on
293 probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
294 end
295 end
296 chip drivers/intel/dptf
297 ## sensor information
298 register "options.tsr[0].desc" = ""DDR""
299 register "options.tsr[1].desc" = ""charger""
300 register "options.tsr[2].desc" = ""ambient""
301
302 ## Active Policy
303 register "policies.active" = "{
304 [0] = {
305 .target = DPTF_CPU,
306 .thresholds = {
307 TEMP_PCT(70, 100),
308 TEMP_PCT(60, 65),
309 TEMP_PCT(42, 58),
310 TEMP_PCT(39, 53),
311 TEMP_PCT(38, 47),
312 TEMP_PCT(35, 43),
313 TEMP_PCT(31, 30),
314 }
315 },
316 [1] = {
317 .target = DPTF_TEMP_SENSOR_0,
318 .thresholds = {
319 TEMP_PCT(60, 100),
320 TEMP_PCT(55, 65),
321 TEMP_PCT(52, 58),
322 TEMP_PCT(50, 53),
323 TEMP_PCT(48, 47),
324 TEMP_PCT(45, 43),
325 TEMP_PCT(41, 30),
326 }
327 }
328 }"
329
330 ## Passive Policy
331 register "policies.passive" = "{
332 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
333 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
334 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
335 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
336 }"
337
338 ## Critical Policy
339 register "policies.critical" = "{
340 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
341 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
342 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
343 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
344 }"
345
346 register "controls.power_limits" = "{
347 .pl1 = {
348 .min_power = 15000,
349 .max_power = 20000,
350 .time_window_min = 28 * MSECS_PER_SEC,
351 .time_window_max = 28 * MSECS_PER_SEC,
352 .granularity = 500
353 },
354 .pl2 = {
355 .min_power = 35000,
356 .max_power = 35000,
357 .time_window_min = 32 * MSECS_PER_SEC,
358 .time_window_max = 32 * MSECS_PER_SEC,
359 .granularity = 500
360 }
361 }"
362
363 ## Charger Performance Control (Control, mA)
364 register "controls.charger_perf" = "{
365 [0] = { 255, 1700 },
366 [1] = { 24, 1500 },
367 [2] = { 16, 1000 },
368 [3] = { 8, 500 }
369 }"
370
371 ## Fan Performance Control (Percent, Speed, Noise, Power)
372 register "controls.fan_perf" = "{
373 [0] = { 100, 6000, 220, 2200, },
374 [1] = { 92, 5500, 180, 1800, },
375 [2] = { 85, 5000, 145, 1450, },
376 [3] = { 70, 4400, 115, 1150, },
377 [4] = { 56, 3900, 90, 900, },
378 [5] = { 45, 3300, 55, 550, },
379 [6] = { 38, 3000, 30, 300, },
380 [7] = { 33, 2900, 15, 150, },
381 [8] = { 10, 800, 10, 100, },
382 [9] = { 0, 0, 0, 50, }
383 }"
384
385 ## Fan options
386 register "options.fan.fine_grained_control" = "1"
387 register "options.fan.step_size" = "2"
388
389 device generic 1 on
390 probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
391 end
392 end
393 end
394 device ref tcss_xhci on
395 chip drivers/usb/acpi
396 device ref tcss_root_hub on
397 chip drivers/usb/acpi
398 register "desc" = ""USB3 Type-C Port C0 (MLB)""
399 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
400 register "use_custom_pld" = "true"
401 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
402 device ref tcss_usb3_port1 on end
403 end
404 end
405 end
406 end
407 device ref xhci on
408 chip drivers/usb/acpi
409 device ref xhci_root_hub on
410 chip drivers/usb/acpi
411 register "desc" = ""USB2 Type-C Port C0 (MLB)""
412 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
413 register "use_custom_pld" = "true"
414 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
415 device ref usb2_port5 on end
416 end
417 chip drivers/usb/acpi
418 register "desc" = ""USB2 Type-A Port A0 (DB)""
419 register "type" = "UPC_TYPE_A"
420 register "use_custom_pld" = "true"
421 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
422 device ref usb2_port1 on end
423 end
424 chip drivers/usb/acpi
425 register "desc" = ""USB2 Type-A Port A1 (DB)""
426 register "type" = "UPC_TYPE_A"
427 register "use_custom_pld" = "true"
428 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
429 device ref usb2_port2 on end
430 end
431 chip drivers/usb/acpi
432 register "desc" = ""USB2 Camera""
433 register "type" = "UPC_TYPE_INTERNAL"
434 device ref usb2_port3 on end
435 end
436 chip drivers/usb/acpi
437 register "desc" = ""USB2 Bluetooth""
438 register "type" = "UPC_TYPE_INTERNAL"
439 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
440 device ref usb2_port10 on end
441 end
442 chip drivers/usb/acpi
443 register "desc" = ""USB3 Type-A Port A0 (MLB)""
444 register "type" = "UPC_TYPE_USB3_A"
445 register "use_custom_pld" = "true"
446 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
447 device ref usb3_port1 on end
448 end
449 chip drivers/usb/acpi
450 register "desc" = ""USB3 Type-A Port A1 (DB)""
451 register "type" = "UPC_TYPE_USB3_A"
452 register "use_custom_pld" = "true"
453 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
454 device ref usb3_port2 on end
455 end
456 end
457 end
458 end
459 device ref shared_sram on end
460 device ref cnvi_wifi on
461 chip drivers/wifi/generic
462 register "wake" = "GPE0_PME_B0"
463 register "enable_cnvi_ddr_rfim" = "true"
464 register "add_acpi_dma_property" = "true"
465 device generic 0 on end
466 end
467 end
468 device ref i2c0 on
469 chip drivers/i2c/tpm
470 register "hid" = ""GOOG0005""
471 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)"
472 device i2c 50 on end
473 end
474 end #I2C0
475 device ref i2c1 on
476 chip drivers/i2c/generic
477 register "hid" = ""ELAN0000""
478 register "desc" = ""ELAN Touchpad""
479 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
480 register "wake" = "GPE0_DW1_03"
481 register "detect" = "1"
482 device i2c 15 on end
483 end
484 end #I2C1
485 device ref i2c5 on
486 chip drivers/i2c/hid
487 register "generic.hid" = ""ELAN9004""
488 register "generic.desc" = ""ELAN Touchscreen""
489 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
490 register "generic.detect" = "1"
491 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
492 register "generic.reset_delay_ms" = "20"
493 register "generic.reset_off_delay_ms" = "2"
494 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
495 register "generic.enable_delay_ms" = "1"
496 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
497 register "generic.stop_delay_ms" = "150"
498 register "generic.stop_off_delay_ms" = "2"
499 register "generic.has_power_resource" = "1"
500 register "hid_desc_reg_offset" = "0x01"
501 device i2c 10 on end
502 end
503 end #I2C5
504 device ref heci1 on end
505 device ref emmc on
506 probe STORAGE STORAGE_UNKNOWN
507 probe STORAGE STORAGE_EMMC
508 end
509 device ref ufs on
510 probe STORAGE STORAGE_UNKNOWN
511 probe STORAGE STORAGE_UFS
512 end
513 device ref uart0 on end
514 device ref pch_espi on
515 chip ec/google/chromeec
516 device pnp 0c09.0 on end
517 end
518 end
519 device ref pmc hidden end
520 device ref hda on
521 chip drivers/sof
522 register "spkr_tplg" = "max98360a"
523 register "jack_tplg" = "rt5682"
524 register "mic_tplg" = "_2ch_pdm0"
525 device generic 0 on end
526 end
527 end
528 end
529 end
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