src/mainboard/google/brya/variants/pirrha/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A14 : USB_C0_AUX_DC_P */
  11         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6),
  12         /* A15 : USB_C0_AUX_DC_N */
  13         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6),
  14
  15         /* B11 : PMCALERT# ==> EN_PP3300_WLAN */
  16         PAD_CFG_GPO(GPP_B11, 1, DEEP),
  17
  18         /* D6  : WWAN_EN ==> NC */
  19         PAD_NC(GPP_D6, NONE),
  20         /* D7  : WLAN_CLKREQ_ODL ==> NC */
  21         PAD_NC(GPP_D7, NONE),
  22         /* D8  : SD_CLKREQ_ODL ==> NC */
  23         PAD_NC(GPP_D8, NONE),
  24
  25         /* E14 : EDP_HPD ==> NC */
  26         PAD_NC(GPP_E14, NONE),
  27         /* E20 : HDMI_DDC_SCL ==> NC */
  28         PAD_NC(GPP_E20, NONE),
  29         /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
  30         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  31         /* E22 : DDPA_CTRLCLK ==> LCD_RST_N - used for MIPI Power seq. */
  32         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
  33         /* E23 : NC */
  34         PAD_NC(GPP_E23, NONE),
  35
  36         /* F6  : NC */
  37         PAD_NC(GPP_F6, NONE),
  38         /* F12 : GSXDOUT ==> EMR_INT_ODL */
  39         PAD_CFG_GPI_INT(GPP_F12, NONE, PLTRST, LEVEL),
  40         /* F13 : SOC_PEN_DETECT_R_ODL ==> NC */
  41         PAD_NC(GPP_F13, NONE),
  42         /* F15 : SOC_PEN_DETECT_OEL ==> NC */
  43         PAD_NC(GPP_F15, NONE),
  44         /* F16 : GSXCLK ==> EMR_RESET_L */
  45         PAD_CFG_GPO(GPP_F16, 0, DEEP),
  46
  47         /* H3  : NC */
  48         PAD_NC(GPP_H3, NONE),
  49         /* H8  : I2C4_SDA ==> SOC_I2C_EMR_SDA */
  50         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
  51         /* H9  : I2C4_SCL ==> SOC_I2C_EMR_SCL */
  52         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
  53         /* H12 : SD_PERST_L ==> NC */
  54         PAD_NC(GPP_H12, NONE),
  55         /* H19 : NC */
  56         PAD_NC(GPP_H19, NONE),
  57         /* H20 : NC */
  58         PAD_NC(GPP_H20, NONE),
  59
  60         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  61         /* BT_I2S_BCLK */
  62         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  63         /* BT_I2S_SYNC */
  64         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  65         /* BT_I2S_SDO */
  66         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  67         /* BT_I2S_SDI */
  68         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  69         /* SSP2_SCLK */
  70         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  71         /* SSP2_SFRM */
  72         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  73         /* SSP_TXD */
  74         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  75         /* SSP_RXD */
  76         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  77 };
  78
  79 /* Early pad configuration in bootblock for pirrha */
  80 static const struct pad_config early_gpio_table[] = {
  81         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
  82         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  83         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
  84         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
  85         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  86         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  87         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
  88         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  89         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
  90         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  91         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
  92         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  93         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
  94         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  95         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
  96         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  97 };
  98
  99 const struct pad_config *variant_gpio_override_table(size_t *num)
 100 {
 101         *num = ARRAY_SIZE(override_gpio_table);
 102         return override_gpio_table;
 103 }
 104
 105 const struct pad_config *variant_early_gpio_table(size_t *num)
 106 {
 107         *num = ARRAY_SIZE(early_gpio_table);
 108         return early_gpio_table;
 109 }