src/mainboard/google/brya/variants/rull/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A7  : NC ==> LTE_Present */
  11         PAD_CFG_GPI(GPP_A7, NONE, DEEP),
  12         /* A8  : GPP_A8 ==> NC */
  13         PAD_NC_LOCK(GPP_A8, NONE, LOCK_CONFIG),
  14         /* A11 : GPP_A11 ==> EN_SPK_PA */
  15         PAD_CFG_GPO(GPP_A11, 0, DEEP),
  16         /* A18 : NC ==> HDMI_HPD_SRC*/
  17         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  18
  19         /* A20 : DDSP_HPD2 ==> NC */
  20         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  21         /* A21 : GPP_A21 ==> NC */
  22         PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
  23         /* A22 : GPP_A22 ==> NC */
  24         PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
  25
  26         /* B5  : I2C2_SDA ==> NA */
  27         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  28         /* B6  : I2C2_SCL ==> NA */
  29         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  30         /* B11 : NC ==> EN_PP3300_WLAN_X*/
  31         PAD_CFG_GPO(GPP_B11, 1, DEEP),
  32
  33         /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */
  34         PAD_CFG_GPO(GPP_D11, 1, DEEP),
  35         /* B4  : SSD_PERST_L */
  36         PAD_CFG_GPO(GPP_B4, 1, DEEP),
  37
  38         /* D3 : ISH_GP3 ==> NA */
  39         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  40         /* D6 : WWAN_PWR_ENABLE ==> PCIE_REFCLK_SSD1_REQ_N */
  41         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  42         /* D8  : SRCCLKREQ3# ==> NC */
  43         PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
  44
  45         /* D13 : EN_PP1800_WCAM_X ==> NA */
  46         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  47         /* D15 : EN_PP2800_WCAM_X ==> NA */
  48         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  49     /* D16 : EN_PP1800_PP1200_WCAM_X ==> NA */
  50         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  51
  52         /* E4  : NA ==> SSD/EMMC/UFS ID */
  53         PAD_CFG_GPI_LOCK(GPP_E4, NONE, LOCK_CONFIG),
  54         /* E5  : NA ==> SSD/EMMC/UFS ID */
  55         PAD_CFG_GPI_LOCK(GPP_E5, NONE, LOCK_CONFIG),
  56         /* E20 : DDP2_CTRLCLK ==> NC */
  57         PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
  58         /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
  59         PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  60
  61         /* F11 : WWAN_PWR_ON ==> NC */
  62         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  63         /* F12 : WWAN_RST_L ==> NA */
  64         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  65         /* F13 : SOC_PEN_DETECT_R_ODL ==> NA */
  66         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  67         /* F15 : SOC_PEN_DETECT_ODL ==> NA */
  68         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  69         /* F23 : V1P05_CTRL ==> NC*/
  70         PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
  71
  72
  73         /* H12 : UART0_RTS# ==> NC*/
  74         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  75         /* H13 : UART0_CTS# ==> NC */
  76         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  77         /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
  78         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  79         /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
  80         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  81     /* H22 : WCAM_MCLK_R ==> NA */
  82         PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG),
  83         /* H23 : WWAN_SAR_DETECT_ODL ==> NA */
  84         PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
  85         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
  86         PAD_CFG_GPO(GPP_H20, 1, DEEP),
  87
  88         /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
  89         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
  90         /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
  91         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
  92
  93         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  94         /* BT_I2S_BCLK */
  95         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  96         /* BT_I2S_SYNC */
  97         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  98         /* BT_I2S_SDO */
  99         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
 100         /* BT_I2S_SDI */
 101         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
 102         /* SSP2_SCLK */
 103         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
 104         /* SSP2_SFRM */
 105         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
 106         /* SSP_TXD */
 107         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
 108         /* SSP_RXD */
 109         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
 110 };
 111
 112 /* Early pad configuration in bootblock */
 113 static const struct pad_config early_gpio_table[] = {
 114         /* B4  : I2C2_SDA ==> SSD1_RST_L */
 115         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 116         /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */
 117         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 118
 119         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 120         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 121
 122     /* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
 123         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 124         /* C1  : SMBDATA ==> TCHSCR_RST_L */
 125         PAD_CFG_GPO(GPP_C1, 1, DEEP),
 126
 127         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 128         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 129
 130         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 131         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 132         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 133         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 134
 135         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 136         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 137         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 138         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 139     /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 140         PAD_CFG_GPO(GPP_H20, 0, DEEP),
 141 };
 142
 143 static const struct pad_config romstage_gpio_table[] = {
 144 };
 145
 146 const struct pad_config *variant_gpio_override_table(size_t *num)
 147 {
 148         *num = ARRAY_SIZE(override_gpio_table);
 149         return override_gpio_table;
 150 }
 151
 152 const struct pad_config *variant_early_gpio_table(size_t *num)
 153 {
 154         *num = ARRAY_SIZE(early_gpio_table);
 155         return early_gpio_table;
 156 }
 157
 158 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 159 {
 160         *num = ARRAY_SIZE(romstage_gpio_table);
 161         return romstage_gpio_table;
 162 }