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soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / brya / variants / rull / overridetree.cb
blobd51fe0b659d1b6c4959015f65f927dff53290927
1 fw_config
2 field THERMAL 18 18
3 option THERMAL_6W 0
4 option THERMAL_15W 1
5 end
6 field WIFI 8 9
7 option WIFI_CNVI_WIFI6E 0
8 option WIFI_PCIE_WIFI7 1
9 end
10
11 end
12
13 chip soc/intel/alderlake
14 register "sagv" = "SaGv_Enabled"
15
16 # EMMC Tx CMD Delay
17 # Refer to EDS-Vol2-42.3.7.
18 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
19 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
20 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
21
22 # EMMC TX DATA Delay 1
23 # Refer to EDS-Vol2-42.3.8.
24 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
25 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
26 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
27
28 # EMMC TX DATA Delay 2
29 # Refer to EDS-Vol2-42.3.9.
30 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
31 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
32 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
33 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
34 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
35
36 # EMMC RX CMD/DATA Delay 1
37 # Refer to EDS-Vol2-42.3.10.
38 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
39 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
40 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
41 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
42 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
43
44 # EMMC RX CMD/DATA Delay 2
45 # Refer to EDS-Vol2-42.3.12.
46 # [17:16] stands for Rx Clock before Output Buffer,
47 # 00: Rx clock after output buffer,
48 # 01: Rx clock before output buffer,
49 # 10: Automatic selection based on working mode.
50 # 11: Reserved
51 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
52 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
53 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
54
55 # EMMC Rx Strobe Delay
56 # Refer to EDS-Vol2-42.3.11.
57 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
58 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
59 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
60
61 # SOC Aux orientation override:
62 # This is a bitfield that corresponds to up to 4 TCSS ports.
63 # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
64 # TcssAuxOri = 0100b
65 # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
66 # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
67 # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
68 # motherboard to USBC connector
69 register "tcss_aux_ori" = "5"
70
71 register "typec_aux_bias_pads[0]" = "{
72 .pad_auxp_dc = GPP_A19,
73 .pad_auxn_dc = GPP_A20
74 }"
75
76 register "typec_aux_bias_pads[1]" = "{
77 .pad_auxp_dc = GPP_E22,
78 .pad_auxn_dc = GPP_E23
79 }"
80
81 # FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn
82 # bypass rails implemented.
83 register "ext_fivr_settings" = "{
84 .configure_ext_fivr = 0,
85 }"
86
87 # Enable the Cnvi BT Audio Offload
88 register "cnvi_bt_audio_offload" = "1"
89
90 # Intel Common SoC Config
91 #+-------------+------------------------------+
92 #| Field | Value |
93 #+-------------+------------------------------+
94 #| I2C0 | TPM. Early init is |
95 #| | required to set up a BAR |
96 #| | for TPM communication |
97 #| I2C1 | Touchscreen |
98 #| I2C3 | Audio |
99 #| I2C5 | Trackpad |
100 #+-------------+------------------------------+
101 register "common_soc_config" = "{
102 .i2c[0] = {
103 .early_init = 1,
104 .speed = I2C_SPEED_FAST_PLUS,
105 .speed_config[0] = {
106 .speed = I2C_SPEED_FAST_PLUS,
107 .scl_lcnt = 55,
108 .scl_hcnt = 30,
109 .sda_hold = 7,
110 }
111 },
112 .i2c[1] = {
113 .speed = I2C_SPEED_FAST,
114 .speed_config[0] = {
115 .speed = I2C_SPEED_FAST,
116 .scl_lcnt = 160,
117 .scl_hcnt = 79,
118 .sda_hold = 7,
119 }
120 },
121 .i2c[3] = {
122 .speed = I2C_SPEED_FAST,
123 .speed_config[0] = {
124 .speed = I2C_SPEED_FAST,
125 .scl_lcnt = 157,
126 .scl_hcnt = 79,
127 .sda_hold = 7,
128 }
129 },
130 .i2c[5] = {
131 .speed = I2C_SPEED_FAST,
132 .speed_config[0] = {
133 .speed = I2C_SPEED_FAST,
134 .scl_lcnt = 152,
135 .scl_hcnt = 79,
136 .sda_hold = 7,
137 }
138 },
139 }"
140
141 # Power limit config
142 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
143 .tdp_pl1_override = 15,
144 .tdp_pl2_override = 25,
145 .tdp_pl4 = 78,
146 }"
147
148 device domain 0 on
149 device ref dtt on
150 chip drivers/intel/dptf
151 ## sensor information
152 register "options.tsr[0].desc" = ""CPU_VR""
153 register "options.tsr[1].desc" = ""CPU""
154 register "options.tsr[2].desc" = ""Ambient""
155 register "options.tsr[3].desc" = ""Charger""
156
157 # TODO: below values are initial reference values only
158 ## Passive Policy
159 register "policies.passive" = "{
160 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
161 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
162 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
163 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
164 [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000),
165 }"
166
167 ## Critical Policy
168 register "policies.critical" = "{
169 [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
170 [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
171 }"
172
173 register "controls.power_limits" = "{
174 .pl1 = {
175 .min_power = 6000,
176 .max_power = 15000,
177 .time_window_min = 28 * MSECS_PER_SEC,
178 .time_window_max = 32 * MSECS_PER_SEC,
179 .granularity = 200
180 },
181 .pl2 = {
182 .min_power = 25000,
183 .max_power = 25000,
184 .time_window_min = 28 * MSECS_PER_SEC,
185 .time_window_max = 32 * MSECS_PER_SEC,
186 .granularity = 1000
187 }
188 }"
189
190 ## Charger Performance Control (Control, mA)
191 register "controls.charger_perf" = "{
192 [0] = { 255, 3000 },
193 [1] = { 24, 1500 },
194 [2] = { 16, 1000 },
195 [3] = { 8, 500 }
196 }"
197
198 device generic 0 on end
199 end
200 end
201 device ref igpu on
202 chip drivers/gfx/generic
203 register "device_count" = "4"
204 # DDIA for eDP
205 register "device[0].name" = ""LCD0""
206 # Internal panel on the first port of the graphics chip
207 register "device[0].type" = "panel"
208 # DDIB for HDMI
209 # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
210 register "device[1].name" = ""DD01""
211 # TCP0 (DP-1) for port C0
212 register "device[2].name" = ""DD02""
213 register "device[2].use_pld" = "true"
214 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
215 # TCP1 (DP-2) for port C1
216 register "device[3].name" = ""DD03""
217 register "device[3].use_pld" = "true"
218 register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
219 device generic 0 on end
220 end
221 end
222 device ref i2c1 on
223 chip drivers/i2c/hid
224 register "generic.hid" = ""ELAN9004""
225 register "generic.desc" = ""ELAN Touchscreen""
226 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
227 register "generic.detect" = "1"
228 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
229 register "generic.reset_delay_ms" = "20"
230 register "generic.reset_off_delay_ms" = "2"
231 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
232 register "generic.stop_delay_ms" = "150"
233 register "generic.stop_off_delay_ms" = "2"
234 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
235 register "generic.enable_delay_ms" = "1"
236 register "generic.has_power_resource" = "1"
237 register "hid_desc_reg_offset" = "0x01"
238 device i2c 10 on end
239 end
240 end
241 device ref i2c3 on
242 chip drivers/i2c/rt5645
243 register "hid" = ""10EC5650""
244 register "name" = ""RT58""
245 register "desc" = ""Realtek RT5650""
246 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
247 register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
248 register "jd_mode" = "2"
249 device i2c 1a on end
250 end
251 end
252 device ref i2c5 on
253 chip drivers/i2c/hid
254 register "generic.hid" = ""SYNA0000""
255 register "generic.cid" = ""ACPI0C50""
256 register "generic.desc" = ""Synaptics Touchpad""
257 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
258 register "generic.wake" = "GPE0_DW2_14"
259 register "generic.detect" = "1"
260 register "hid_desc_reg_offset" = "0x20"
261 device i2c 2c on end
262 end
263 chip drivers/i2c/hid
264 register "generic.hid" = ""PNP0C50""
265 register "generic.desc" = ""PIXART Touchpad""
266 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
267 register "generic.wake" = "GPE0_DW2_14"
268 register "generic.detect" = "1"
269 register "hid_desc_reg_offset" = "0x20"
270 device i2c 68 on end
271 end
272 end
273 device ref cnvi_wifi on
274 chip drivers/wifi/generic
275 register "wake" = "GPE0_PME_B0"
276 register "enable_cnvi_ddr_rfim" = "true"
277 register "add_acpi_dma_property" = "true"
278 device generic 0 on end
279 end
280 probe WIFI WIFI_CNVI_WIFI6E
281 probe unprovisioned
282 end
283 device ref pcie_rp4 on
284 # PCIe 4 WLAN
285 register "pch_pcie_rp[PCH_RP(4)]" = "{
286 .clk_src = 2,
287 .clk_req = 2,
288 .flags = PCIE_RP_LTR | PCIE_RP_AER,
289 }"
290 chip drivers/wifi/generic
291 register "wake" = "GPE0_DW1_03"
292 register "add_acpi_dma_property" = "true"
293 device pci 00.0 on end
294 end
295 chip soc/intel/common/block/pcie/rtd3
296 # # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
297 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
298 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
299 register "srcclk_pin" = "2"
300 device generic 0 on end
301 end
302 probe WIFI WIFI_PCIE_WIFI7
303 probe unprovisioned
304 end
305 device ref pch_espi on
306 chip ec/google/chromeec
307 use conn0 as mux_conn[0]
308 use conn1 as mux_conn[1]
309 device pnp 0c09.0 on end
310 end
311 end
312 device ref pmc hidden
313 chip drivers/intel/pmc_mux
314 device generic 0 on
315 chip drivers/intel/pmc_mux/conn
316 use usb2_port1 as usb2_port
317 use tcss_usb3_port2 as usb3_port
318 device generic 0 alias conn0 on end
319 end
320 chip drivers/intel/pmc_mux/conn
321 use usb2_port2 as usb2_port
322 use tcss_usb3_port1 as usb3_port
323 device generic 1 alias conn1 on end
324 end
325 end
326 end
327 end
328 device ref tcss_xhci on
329 chip drivers/usb/acpi
330 device ref tcss_root_hub on
331 chip drivers/usb/acpi
332 register "desc" = ""USB3 Type-C Port C0 (MLB)""
333 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
334 register "use_custom_pld" = "true"
335 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
336 device ref tcss_usb3_port2 on end
337 end
338 chip drivers/usb/acpi
339 register "desc" = ""USB3 Type-C Port C1 (DB)""
340 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
341 register "use_custom_pld" = "true"
342 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
343 device ref tcss_usb3_port1 on end
344 end
345 end
346 end
347 end
348 device ref xhci on
349 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
350 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
351 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
352 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
353 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
354 register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
355 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
356 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
357
358 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)
359 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
360 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
361 chip drivers/usb/acpi
362 device ref xhci_root_hub on
363 chip drivers/usb/acpi
364 register "desc" = ""USB2 Type-C Port C0 (MLB)""
365 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
366 register "use_custom_pld" = "true"
367 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
368 device ref usb2_port1 on end
369 end
370 chip drivers/usb/acpi
371 register "desc" = ""USB2 Type-C Port C1 (DB)""
372 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
373 register "use_custom_pld" = "true"
374 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
375 device ref usb2_port2 on end
376 end
377 chip drivers/usb/acpi
378 register "desc" = ""USB2 Type-A Port A0 (MLB)""
379 register "type" = "UPC_TYPE_A"
380 register "use_custom_pld" = "true"
381 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
382 device ref usb2_port3 on end
383 end
384 chip drivers/usb/acpi
385 register "desc" = ""USB2 Type-A Port A1 (DB)""
386 register "type" = "UPC_TYPE_A"
387 register "use_custom_pld" = "true"
388 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
389 device ref usb2_port4 on end
390 end
391 chip drivers/usb/acpi
392 register "desc" = ""USB2 LTE""
393 register "type" = "UPC_TYPE_INTERNAL"
394 device ref usb2_port5 on end
395 end
396 chip drivers/usb/acpi
397 register "desc" = ""USB2 UFC""
398 register "type" = "UPC_TYPE_INTERNAL"
399 device ref usb2_port6 on end
400 end
401 chip drivers/usb/acpi
402 register "desc" = ""PCIe Bluetooth""
403 register "type" = "UPC_TYPE_INTERNAL"
404 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
405 device ref usb2_port8 on end
406 end
407 chip drivers/usb/acpi
408 register "desc" = ""CNVi Bluetooth""
409 register "type" = "UPC_TYPE_INTERNAL"
410 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
411 device ref usb2_port10 on
412 probe WIFI WIFI_CNVI_WIFI6E
413 end
414 end
415 chip drivers/usb/acpi
416 register "desc" = ""USB3 Type-A Port A0 (MLB)""
417 register "type" = "UPC_TYPE_USB3_A"
418 register "use_custom_pld" = "true"
419 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
420 device ref usb3_port1 on end
421 end
422 chip drivers/usb/acpi
423 register "desc" = ""USB3 Type-A Port A1 (DB)""
424 register "type" = "UPC_TYPE_USB3_A"
425 register "use_custom_pld" = "true"
426 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
427 device ref usb3_port2 on end
428 end
429 chip drivers/usb/acpi
430 register "desc" = ""USB3 WWAN""
431 register "type" = "UPC_TYPE_INTERNAL"
432 device ref usb3_port3 on end
433 end
434 chip drivers/usb/acpi
435 register "desc" = ""USB3 WLAN""
436 register "type" = "UPC_TYPE_INTERNAL"
437 device ref usb3_port4 on end
438 end
439 end
440 end
441 end
442 device ref pcie_rp7 off end # SDCard
443 device ref pcie_rp9 on
444 # Enable NVMe SSD PCIe 9-12 using clk 1
445 register "pch_pcie_rp[PCH_RP(9)]" = "{
446 .clk_src = 1,
447 .clk_req = 1,
448 .flags = PCIE_RP_LTR | PCIE_RP_AER,
449 .pcie_rp_aspm = ASPM_L1,
450 }"
451 chip soc/intel/common/block/pcie/rtd3
452 # enable_gpio is EN_PP3300_SSD
453 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
454 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
455 register "srcclk_pin" = "1"
456 device generic 0 on
457 probe STORAGE STORAGE_NVME
458 probe unprovisioned
459 end
460 end
461 end
462 device ref emmc on
463 probe STORAGE STORAGE_EMMC
464 probe unprovisioned
465 end
466 device ref hda on
467 chip drivers/sof
468 register "spkr_tplg" = "rt5650_sp"
469 register "jack_tplg" = "rt5650_hp"
470 register "mic_tplg" = "_2ch_pdm0"
471 device generic 0 on end
472 end
473 end
474 end
475 end
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