src/mainboard/google/brya/variants/sundance/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7 #include <fw_config.h>
   8
   9 /* Pad configuration in ramstage for Sundance */
  10 static const struct pad_config override_gpio_table[] = {
  11         /* A8  : WWAN_RF_DISABLE_ODL */
  12         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  13         /* A20  : NC */
  14         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  15         /* B5  : NC */
  16         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  17         /* B6  : NC */
  18         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  19         /* D3  : WCAM_RST_L ==> NC */
  20         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  21         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  22         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  23         /* D8  : NC */
  24         PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
  25         /* D15  : EN_PP2800_WCAM_X ==> NC */
  26         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  27         /* D16  : EN_PP1800_PP1200_WCAM_X ==> NC */
  28         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  29         /* D17 : NC ==> SD_WAKE_N */
  30         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  31         /* E20  : NC */
  32         PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
  33         /* E21  : NC */
  34         PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  35         /* F12 : WWAN_RST_L */
  36         PAD_CFG_GPO(GPP_F12, 1, DEEP),
  37         /* F13  : NC */
  38         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  39         /* F15  : NC */
  40         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  41         /* H12  : NC */
  42         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  43         /* H13  : NC */
  44         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  45         /* H19  : NC */
  46         PAD_NC_LOCK(GPP_H19, NONE, LOCK_CONFIG),
  47         /* H22  : WCAM_MCLK_R ==> NC */
  48         PAD_NC(GPP_H22, NONE),
  49         /* H23 : WWAN_SAR_DETECT_ODL ==> NC */
  50         PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
  51 };
  52
  53 /* Early pad configuration in bootblock */
  54 static const struct pad_config early_gpio_table[] = {
  55         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
  56         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  57         /*
  58         * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
  59         * requirement. WWAN_EN must be asserted before WWAN_RST_L is released
  60         * (with min delay 0 ms), so this works as long as the pin used for
  61         * WWAN_EN comes before the pin used for WWAN_RST_L.
  62         */
  63         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  64         PAD_CFG_GPO(GPP_D6, 0, DEEP),
  65         /* F12 : WWAN_RST_L */
  66         PAD_CFG_GPO(GPP_F12, 0, DEEP),
  67         /* Enable touchscreen, hold in reset */
  68         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
  69         PAD_CFG_GPO(GPP_C0, 0, DEEP),
  70         /* C1  : SMBDATA ==> USI_RST_L */
  71         PAD_CFG_GPO(GPP_C1, 0, DEEP),
  72         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
  73         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
  74         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  75         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  76         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
  77         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  78         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
  79         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  80         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
  81         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  82         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
  83         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  84 };
  85
  86 /* Pad configuration in romstage for Sundance */
  87 static const struct pad_config romstage_gpio_table[] = {
  88         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  89         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  90         /* Enable touchscreen, hold in reset */
  91         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
  92         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  93 };
  94
  95 const struct pad_config *variant_gpio_override_table(size_t *num)
  96 {
  97         *num = ARRAY_SIZE(override_gpio_table);
  98         return override_gpio_table;
  99 }
 100
 101 const struct pad_config *variant_early_gpio_table(size_t *num)
 102 {
 103
 104         *num = ARRAY_SIZE(early_gpio_table);
 105         return early_gpio_table;
 106 }
 107
 108 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 109 {
 110         *num = ARRAY_SIZE(romstage_gpio_table);
 111         return romstage_gpio_table;
 112 }