soc/intel/ptl: Update ME specification version to 21

[coreboot.git] / src / mainboard / google / brya / variants / sundance / overridetree.cb

fw_config
        field WWAN 3 4
                option LTE_ABSENT               0
                option LTE_PRESENT              1
        end
        field WIFI_SAR_ID 12 15
                option WIFI_SAR_TABLE_AX211     0
        end
end

chip soc/intel/alderlake
        # Acoustic settings
        register "acoustic_noise_mitigation" = "1"
        register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
        register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
        register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
        register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
        register "PreWake" = "100"

        register "sagv" = "SaGv_Enabled"

        # EMMC Tx CMD Delay
        # Refer to EDS-Vol2-42.3.7.
        # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39, total 625ps.
        # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39, total 625ps.
        register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"

        # EMMC TX DATA Delay 1
        # Refer to EDS-Vol2-42.3.8.
        # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78, total 465ps.
        # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79, total 465ps.
        register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"

        # EMMC TX DATA Delay 2
        # Refer to EDS-Vol2-42.3.9.
        # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79, total 3500ps.
        # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 5250ps.
        # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79, total 5000ps.
        # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79, total 5000ps.
        register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"

        # EMMC RX CMD/DATA Delay 1
        # Refer to EDS-Vol2-42.3.10.
        # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119, total 3500ps.
        # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 3375ps.
        # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119, total 3250ps.
        # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119, total 3375ps.
        register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B"

        # EMMC RX CMD/DATA Delay 2
        # Refer to EDS-Vol2-42.3.12.
        # [17:16] stands for Rx Clock before Output Buffer,
        #         00: Rx clock after output buffer,
        #         01: Rx clock before output buffer,
        #         10: Automatic selection based on working mode.
        #         11: Reserved
        # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39, total 0ps.
        # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79, total 5000ps.
        register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028"

        # EMMC Rx Strobe Delay
        # Refer to EDS-Vol2-42.3.11.
        # [14:8] Rx Strobe Delay DLL 1 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps.
        # [6:0] Rx Strobe Delay DLL 2 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps.
        register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"

        # SOC Aux orientation override:
        # This is a bitfield that corresponds to up to 4 TCSS ports.
        # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
        # TcssAuxOri = 0101b
        # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
        # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
        # motherboard to USBC connector
        register "tcss_aux_ori" = "5"

        register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
        register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"

        register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C0
        register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C1
        register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"     # WWAN
        register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # WFC Camera
        register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth port for PCIe WLAN
        register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth port for CNVi WLAN

        register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN

        # Configure external V1P05/Vnn/VnnSx Rails for Sundance
        register "ext_fivr_settings" = "{
                .configure_ext_fivr = 1,
                .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
                .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
                .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
                .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
                .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
                .v1p05_voltage_mv = 1050,
                .vnn_voltage_mv = 780,
                .vnn_sx_voltage_mv = 1050,
                .v1p05_icc_max_ma = 500,
                .vnn_icc_max_ma = 500,
        }"

        # Intel Common SoC Config
        #+-------------------+---------------------------+
        #| Field             |  Value                    |
        #+-------------------+---------------------------+
        #| I2C0              | TPM. Early init is        |
        #|                   | required to set up a BAR  |
        #|                   | for TPM communication     |
        #| I2C1              | Touchscreen               |
        #| I2C3              | Audio                     |
        #| I2C5              | Trackpad                  |
        #+-------------------+---------------------------+
        register "common_soc_config" = "{
                .i2c[0] = {
                        .early_init = 1,
                        .speed = I2C_SPEED_FAST_PLUS,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST_PLUS,
                                .scl_lcnt = 55,
                                .scl_hcnt = 30,
                                .sda_hold = 7,
                        }
                },
                .i2c[1] = {
                        .speed = I2C_SPEED_FAST,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST,
                                .scl_lcnt = 157,
                                .scl_hcnt = 79,
                                .sda_hold = 13,
                        }
                },
                .i2c[3] = {
                        .speed = I2C_SPEED_FAST,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST,
                                .scl_lcnt = 158,
                                .scl_hcnt = 79,
                                .sda_hold = 7,
                        }
                },
                .i2c[5] = {
                        .speed = I2C_SPEED_FAST,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST,
                                .scl_lcnt = 158,
                                .scl_hcnt = 79,
                                .sda_hold = 7,
                        }
                },
        }"

        device domain 0 on
                device ref dtt on
                        chip drivers/intel/dptf
                                ## sensor information
                                register "options.tsr[0].desc" = ""CPU""
                                register "options.tsr[1].desc" = ""DDR""
                                register "options.tsr[2].desc" = ""5VCharger""


                                ## Passive Policy
                                register "policies.passive" = "{
                                        [0] = DPTF_PASSIVE(CPU,         CPU,           90, 10000),
                                        [1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 60000),
                                        [2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 60000),
                                        [3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 15000),
                                }"

                                ## Critical Policy
                                register "policies.critical" = "{
                                        [0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
                                        [1] = DPTF_CRITICAL(TEMP_SENSOR_0,     100, SHUTDOWN),
                                        [2] = DPTF_CRITICAL(TEMP_SENSOR_1,     100, SHUTDOWN),
                                        [3] = DPTF_CRITICAL(TEMP_SENSOR_2,     100, SHUTDOWN),
                                }"

                                register "controls.power_limits" = "{
                                        .pl1 = {
                                                        .min_power = 3000,
                                                        .max_power = 6000,
                                                        .time_window_min = 1 * MSECS_PER_SEC,
                                                        .time_window_max = 1 * MSECS_PER_SEC,
                                                        .granularity = 200,
                                                },
                                        .pl2 = {
                                                        .min_power = 25000,
                                                        .max_power = 25000,
                                                        .time_window_min = 1 * MSECS_PER_SEC,
                                                        .time_window_max = 1 * MSECS_PER_SEC,
                                                        .granularity = 1000,
                                                }
                                }"

                                ## Charger Performance Control (Control, mA)
                                register "controls.charger_perf" = "{
                                        [0] = { 255, 3000 },
                                        [1] = {  24, 2000 },
                                        [2] = {  16, 1500 },
                                        [3] = {   8, 1000 }
                                }"
                                device generic 0 on end
                        end
                end
                device ref i2c1 on
                        chip drivers/i2c/hid
                                register "generic.hid" = ""GDIX0000""
                                register "generic.desc" = ""Goodix Touchscreen""
                                register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
                                register "generic.detect" = "1"
                                register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
                                register "generic.enable_delay_ms" = "20"
                                register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
                                register "generic.reset_delay_ms" = "180"
                                register "generic.reset_off_delay_ms" = "3"
                                register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
                                register "generic.stop_off_delay_ms" = "1"
                                register "generic.has_power_resource" = "1"
                                register "hid_desc_reg_offset" = "0x01"
                                device i2c 5d on end
                        end
                end
                device ref i2c3 on
                        chip drivers/i2c/generic
                                register "hid" = ""RTL5682""
                                register "name" = ""RT58""
                                register "desc" = ""Headset Codec""
                                register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
                                # Set the jd_src to RT5668_JD1 for jack detection
                                register "property_count" = "1"
                                register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
                                register "property_list[0].name" = ""realtek,jd-src""
                                register "property_list[0].integer" = "1"
                                device i2c 1a on end
                        end
                        chip drivers/generic/alc1015
                                register "hid" = ""RTL1019""
                                register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
                                device generic 0 on end
                        end
                end
                device ref i2c5 on
                        chip drivers/i2c/generic
                                register "hid" = ""ELAN0000""
                                register "desc" = ""ELAN Touchpad""
                                register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
                                register "wake" = "GPE0_DW2_14"
                                register "detect" = "1"
                                device i2c 15 on end
                        end
                        chip drivers/i2c/hid
                                register "generic.hid" = ""FCAL0000""
                                register "generic.cid" = ""ACPI0C50""
                                register "generic.desc" = ""Focal Touchpad""
                                register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
                                register "generic.wake" = "GPE0_DW2_14"
                                register "generic.detect" = "1"
                                register "hid_desc_reg_offset" = "0x01"
                                device i2c 0x38 on end
                        end
                end
                device ref pcie_rp4 on
                        # PCIe 4 WLAN
                        register "pch_pcie_rp[PCH_RP(4)]" = "{
                                .clk_src = 2,
                                .clk_req = 2,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                        }"
                        chip drivers/wifi/generic
                                register "wake" = "GPE0_DW1_03"
                                register "add_acpi_dma_property" = "true"
                                device pci 00.0 on end
                        end
                end
                device ref pcie_rp7 off end
                device ref pch_espi on
                        chip ec/google/chromeec
                                use conn0 as mux_conn[0]
                                use conn1 as mux_conn[1]
                                device pnp 0c09.0 on end
                        end
                end
                device ref pmc hidden
                        chip drivers/intel/pmc_mux
                                device generic 0 on
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port1 as usb2_port
                                                use tcss_usb3_port1 as usb3_port
                                                device generic 0 alias conn0 on end
                                        end
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port2 as usb2_port
                                                use tcss_usb3_port2 as usb3_port
                                                device generic 1 alias conn1 on end
                                        end
                                end
                        end
                end
                device ref tcss_xhci on
                        chip drivers/usb/acpi
                                device ref tcss_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
                                                device ref tcss_usb3_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C1 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
                                                device ref tcss_usb3_port2 on end
                                        end
                                end
                        end
                end
                device ref xhci on
                        chip drivers/usb/acpi
                                device ref xhci_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
                                                device ref usb2_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C1 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
                                                device ref usb2_port2 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 WWAN""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb2_port5 on
                                                        probe WWAN LTE_PRESENT
                                                end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 UFC""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb2_port6 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 WFC""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb2_port7 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Bluetooth""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "reset_gpio" =
                                                        "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
                                                device ref usb2_port8 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""CNVi Bluetooth""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "reset_gpio" =
                                                        "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
                                                device ref usb2_port10 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 WWAN""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb3_port3 on
                                                        probe WWAN LTE_PRESENT
                                                end
                                        end
                                end
                        end
                end
        end
end