src/mainboard/google/brya/variants/taniks/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A6  : ESPI_ALERT1# ==> NC */
  11         PAD_NC(GPP_A6, NONE),
  12         /* A7  : SRCCLK_OE7# ==> NC */
  13         PAD_NC(GPP_A7, NONE),
  14         /* A8  : SRCCLKREQ7# ==> NC */
  15         PAD_NC(GPP_A8, NONE),
  16         /* A12 : SATAXPCIE1 ==> NC */
  17         PAD_NC(GPP_A12, NONE),
  18         /* A14 : USB_OC1# ==> NC */
  19         PAD_NC(GPP_A14, NONE),
  20         /* A15 : USB_OC2# ==> NC */
  21         PAD_NC(GPP_A15, NONE),
  22         /* A18 : DDSP_HPDB ==> NC */
  23         PAD_NC(GPP_A18, NONE),
  24         /* A19 : DDSP_HPD1 ==> NC */
  25         PAD_NC(GPP_A19, NONE),
  26         /* A20 : DDSP_HPD2 ==> NC */
  27         PAD_NC(GPP_A20, NONE),
  28         /* A21 : DDPC_CTRCLK ==> NC */
  29         PAD_NC(GPP_A21, NONE),
  30         /* A22 : DDPC_CTRLDATA ==> NC */
  31         PAD_NC(GPP_A22, NONE),
  32
  33         /* B2  : VRALERT# ==> NC */
  34         PAD_NC(GPP_B2, NONE),
  35         /* B3  : PROC_GP2 ==> NC */
  36         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  37         /* B15 : TIME_SYNC0 ==> NC */
  38         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  39
  40         /* C3 : SML0CLK ==> NC */
  41         PAD_NC(GPP_C3, NONE),
  42         /* C4 : SML0DATA ==> NC */
  43         PAD_NC(GPP_C4, NONE),
  44         /* C6  : SML1CLK ==> NC */
  45         PAD_NC(GPP_C6, NONE),
  46
  47         /* D1  : ISH_GP1 ==> NC */
  48         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  49         /* D2  : ISH_GP2 ==> NC */
  50         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  51         /* D3  : ISH_GP3 ==> NC */
  52         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  53         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
  54         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
  55         /* D9  : ISH_SPI_CS# ==> NC */
  56         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  57         /* D10 : ISH_SPI_CLK ==> NC */
  58         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  59         /* D13 : ISH_UART0_RXD ==> NC */
  60         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  61         /* D14 : ISH_UART0_TXD ==> NC */
  62         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
  63         /* D15 : ISH_UART0_RTS# ==> NC */
  64         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  65         /* D16 : ISH_UART0_CTS# ==> NC */
  66         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  67         /* D17 : UART1_RXD ==> NC */
  68         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  69
  70         /* E0  : SATAXPCIE0 ==> NC */
  71         PAD_NC(GPP_E0, NONE),
  72         /* E3  : PROC_GP0 ==> NC */
  73         PAD_NC(GPP_E3, NONE),
  74         /* E4  : SATA_DEVSLP0 ==> NC */
  75         PAD_NC(GPP_E4, NONE),
  76         /* E5  : SATA_DEVSLP1 ==> NC */
  77         PAD_NC(GPP_E5, NONE),
  78         /* E7  : PROC_GP1 ==> NC */
  79         PAD_NC(GPP_E7, NONE),
  80         /* E10 : THC0_SPI1_CS# ==> NC */
  81         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
  82         /* E16 : RSVD_TP ==> NC */
  83         PAD_NC(GPP_E16, NONE),
  84         /* E17 : THC0_SPI1_INT# ==> NC */
  85         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  86         /* E18 : DDP1_CTRLCLK ==> NC */
  87         PAD_NC(GPP_E18, NONE),
  88         /* E19 : DDP1_CTRLDATA ==> NC */
  89         PAD_NC(GPP_E19, NONE),
  90         /* E20 : DDP2_CTRLCLK ==> NC */
  91         PAD_NC(GPP_E20, NONE),
  92         /* E21 : DDP2_CTRLDATA ==> NC */
  93         PAD_NC(GPP_E21, NONE),
  94
  95         /* F6  : CNV_PA_BLANKING ==> NC */
  96         PAD_NC(GPP_F6, NONE),
  97         /* F11 : THC1_SPI2_CLK ==> NC */
  98         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  99         /* F12 : GSXDOUT ==> NC */
 100         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 101         /* F13 : GSXDOUT ==> NC */
 102         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 103         /* F15 : GSXSRESET# ==> NC */
 104         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 105         /* F16 : GSXCLK ==> NC */
 106         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 107         /* F19 : SRCCLKREQ6# ==> NC */
 108         PAD_NC(GPP_F19, NONE),
 109         /* F20 : EXT_PWR_GATE# ==> NC */
 110         PAD_NC(GPP_F20, NONE),
 111         /* F21 : EXT_PWR_GATE2# ==> NC */
 112         PAD_NC(GPP_F21, NONE),
 113         /* F22 : VNN_CTRL ==> VNN_CTRL */
 114         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 115         /* F23 : BP105_CTRL ==> PP1050_CTRL */
 116         PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 117
 118         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 119         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
 120         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 121         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
 122         /* H8  : I2C4_SDA ==> NC */
 123         PAD_NC(GPP_H8, NONE),
 124         /* H9  : I2C4_SCL ==> NC */
 125         PAD_NC(GPP_H9, NONE),
 126         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 127         PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
 128         /* H15 : DDPB_CTRLCLK ==> NC */
 129         PAD_NC(GPP_H15, NONE),
 130         /* H17 : DDPB_CTRLDATA ==> NC */
 131         PAD_NC(GPP_H17, NONE),
 132         /* H19 : SRCCLKREQ4# ==> NC */
 133         PAD_NC(GPP_H19, NONE),
 134         /* H21 : IMGCLKOUT2 ==>  NC */
 135         PAD_NC(GPP_H21, NONE),
 136         /* H22 : IMGCLKOUT3 ==> NC */
 137         PAD_NC(GPP_H22, NONE),
 138         /* H23 : SRCCLKREQ5# ==> NC */
 139         PAD_NC(GPP_H23, NONE),
 140
 141         /* R7 : I2S2_RXD ==> NC */
 142         PAD_NC(GPP_R7, NONE),
 143
 144         /* S0 : SNDW0_CLK ==> NC */
 145         PAD_NC(GPP_S0, NONE),
 146         /* S1 : SNDW0_DATA ==> NC */
 147         PAD_NC(GPP_S1, NONE),
 148         /* S4 : SNDW2_CLK ==> NC */
 149         PAD_NC(GPP_S4, NONE),
 150         /* S5 : SNDW2_DATA ==> NC */
 151         PAD_NC(GPP_S5, NONE),
 152         /* S6 : SNDW3_CLK ==> NC */
 153         PAD_NC(GPP_S6, NONE),
 154         /* S7 : SNDW3_DATA ==> NC */
 155         PAD_NC(GPP_S7, NONE),
 156
 157         /* GPD11: LANPHYC ==> WWAN_CONFIG1 */
 158         PAD_NC(GPD11, NONE),
 159 };
 160
 161 /* Early pad configuration in bootblock */
 162 static const struct pad_config early_gpio_table[] = {
 163         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 164         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 165         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 166         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 167         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 168         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 169         /* E15 : RSVD_TP ==> PCH_WP_OD */
 170         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 171         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 172         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 173         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 174         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 175         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 176         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 177         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 178         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 179         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 180         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 181         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 182         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 183         /*
 184          * B4  : PROC_GP3 ==> SSD_PERST_L
 185          * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 186          */
 187         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 188         /* CPU PCIe VGPIO for PEG60 */
 189         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 190         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 191         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 192         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 193         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 194         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 195         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 196         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 197         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 198         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 199         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 200         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 201         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 202         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 203         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 204         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 205         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 206         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 207         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 208         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 209 };
 210
 211 static const struct pad_config romstage_gpio_table[] = {
 212         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 213         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 214
 215         /* Enable touchscreen, hold in reset */
 216         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 217         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 218         /* C1  : SMBDATA ==> USI_RST_L */
 219         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 220 };
 221
 222 const struct pad_config *variant_gpio_override_table(size_t *num)
 223 {
 224         *num = ARRAY_SIZE(override_gpio_table);
 225         return override_gpio_table;
 226 }
 227
 228 const struct pad_config *variant_early_gpio_table(size_t *num)
 229 {
 230         *num = ARRAY_SIZE(early_gpio_table);
 231         return early_gpio_table;
 232 }
 233
 234 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 235 {
 236         *num = ARRAY_SIZE(romstage_gpio_table);
 237         return romstage_gpio_table;
 238 }