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soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / dedede / variants / boxy / overridetree.cb
blob36eadcbd1f2aba1921bfdc94f9aae2a9d1a0ec39
1 fw_config
2 field AUDIO_CODEC_SOURCE 41 43
3 option AUDIO_CODEC_ALC5682I_VS 0
4 option AUDIO_CODEC_ALC5682_VD 1
5 end
6 end
7
8
9 chip soc/intel/jasperlake
10
11 # Intel Common SoC Config
12 #+-------------------+---------------------------+
13 #| Field | Value |
14 #+-------------------+---------------------------+
15 #| GSPI0 | cr50 TPM. Early init is |
16 #| | required to set up a BAR |
17 #| | for TPM communication |
18 #| | before memory is up |
19 #| I2C4 | Audio |
20 #+-------------------+---------------------------+
21 register "common_soc_config" = "{
22 .gspi[0] = {
23 .speed_mhz = 1,
24 .early_init = 1,
25 },
26 .i2c[4] = {
27 .speed_config[0] = {
28 .speed = I2C_SPEED_FAST,
29 .scl_lcnt = 190,
30 .scl_hcnt = 100,
31 .sda_hold = 40,
32 }
33 },
34 }"
35
36 # Power limit config
37 register "power_limits_config[JSL_N4500_6W_CORE]" = "{
38 .tdp_pl1_override = 6,
39 .tdp_pl2_override = 20,
40 .tdp_pl4 = 60,
41 }"
42
43 register "power_limits_config[JSL_N5100_6W_CORE]" = "{
44 .tdp_pl1_override = 6,
45 .tdp_pl2_override = 20,
46 .tdp_pl4 = 60,
47 }"
48
49 # Root Port 3 (index 2) for LAN
50 # External PCIe port 7 is mapped to PCIe Root Port 3
51 register "PcieClkSrcUsage[4]" = "2"
52
53 # Root Port 7 (index 6) for WLAN
54 # External PCIe port 3 is mapped to PCIe Root Port 7
55 register "PcieClkSrcUsage[3]" = "6"
56
57 # Audio related configurations
58 register "PchHdaAudioLinkDmicEnable[0]" = "0"
59 register "PchHdaAudioLinkDmicEnable[1]" = "0"
60
61 # Disable SD card
62 register "sdcard_cd_gpio" = "0"
63 register "SdCardPowerEnableActiveHigh" = "0"
64
65 # Disable eDP on port A
66 register "DdiPortAConfig" = "0"
67
68 # Enable HPD and DDC for DDI port A
69 register "DdiPortAHpd" = "1"
70 register "DdiPortADdc" = "1"
71
72 # Does not support external vnn power rail
73 register "disable_external_bypass_vr" = "1"
74
75 # USB Port Configuration
76 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
77 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
78 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
79
80 #Bitmap for Wake Enable on USB attach/detach
81 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
82 USB_PORT_WAKE_ENABLE(2) |
83 USB_PORT_WAKE_ENABLE(3) |
84 USB_PORT_WAKE_ENABLE(4)"
85 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
86 USB_PORT_WAKE_ENABLE(2) |
87 USB_PORT_WAKE_ENABLE(3) |
88 USB_PORT_WAKE_ENABLE(4)"
89
90 device domain 0 on
91 device pci 04.0 on
92 chip drivers/intel/dptf
93 ## Passive Policy
94 register "policies.passive" = "{
95 [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
96 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 60000),
97 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 60000),
98 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 15000)
99 }"
100
101 ## Critical Policy
102 register "policies.critical" = "{
103 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
104 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
105 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
106 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN)
107 }"
108
109 register "controls.power_limits" = "{
110 .pl1 = {
111 .min_power = 3000,
112 .max_power = 6000,
113 .time_window_min = 1 * MSECS_PER_SEC,
114 .time_window_max = 1 * MSECS_PER_SEC,
115 .granularity = 100,
116 },
117 .pl2 = {
118 .min_power = 20000,
119 .max_power = 20000,
120 .time_window_min = 1 * MSECS_PER_SEC,
121 .time_window_max = 1 * MSECS_PER_SEC,
122 .granularity = 1000,
123 }
124 }"
125
126 register "options.tsr[0].desc" = ""Memory""
127 register "options.tsr[1].desc" = ""Power""
128 register "options.tsr[2].desc" = ""Chassis""
129
130 ## Charger Performance Control (Control, mA)
131 register "controls.charger_perf" = "{
132 [0] = { 255, 3000 },
133 [1] = { 24, 1500 },
134 [2] = { 16, 1000 },
135 [3] = { 8, 500 }
136 }"
137
138 device generic 0 on end
139 end
140 end # SA Thermal device
141 device pci 14.0 on
142 chip drivers/usb/acpi
143 device usb 0.0 on
144 chip drivers/usb/acpi
145 register "desc" = ""USB2 Type-C Port C0""
146 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
147 register "group" = "ACPI_PLD_GROUP(1, 1)"
148 device usb 2.0 on end
149 end
150 chip drivers/usb/acpi
151 register "desc" = ""USB2 Type-A Port A0""
152 register "type" = "UPC_TYPE_A"
153 register "group" = "ACPI_PLD_GROUP(1, 3)"
154 device usb 2.1 on end
155 end
156 chip drivers/usb/acpi
157 register "desc" = ""USB2 Type-A Port A1""
158 register "type" = "UPC_TYPE_A"
159 register "group" = "ACPI_PLD_GROUP(1, 2)"
160 device usb 2.2 on end
161 end
162 chip drivers/usb/acpi
163 register "desc" = ""USB2 Type-C Port C1""
164 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
165 register "group" = "ACPI_PLD_GROUP(2, 1)"
166 device usb 2.3 on end
167 end
168 chip drivers/usb/acpi
169 register "desc" = ""USB3 Type-C Port C0""
170 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
171 register "group" = "ACPI_PLD_GROUP(1, 1)"
172 device usb 3.0 on end
173 end
174 chip drivers/usb/acpi
175 register "desc" = ""USB3 Type-C Port C1""
176 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
177 register "group" = "ACPI_PLD_GROUP(2, 1)"
178 device usb 3.1 on end
179 end
180 chip drivers/usb/acpi
181 register "desc" = ""USB3 Type-A Port A0""
182 register "type" = "UPC_TYPE_USB3_A"
183 register "group" = "ACPI_PLD_GROUP(1, 3)"
184 device usb 3.2 on end
185 end
186 chip drivers/usb/acpi
187 register "desc" = ""USB3 Type-A Port A1""
188 register "type" = "UPC_TYPE_USB3_A"
189 register "group" = "ACPI_PLD_GROUP(1, 2)"
190 device usb 3.3 on end
191 end
192 end
193 end
194 end # USB xHCI
195 device pci 15.0 off end # I2C 0
196 device pci 15.1 off end # I2C 1
197 device pci 15.2 off end # I2C 2
198 device pci 15.3 off end # I2C 3
199 device pci 19.0 on
200 chip drivers/i2c/generic
201 register "hid" = ""10EC5682""
202 register "name" = ""RT58""
203 register "desc" = ""Realtek RT5682""
204 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
205 register "property_count" = "1"
206 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
207 register "property_list[0].name" = ""realtek,jd-src""
208 register "property_list[0].integer" = "1"
209 device i2c 1a on
210 probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682_VD
211 end
212 end
213 chip drivers/i2c/generic
214 register "hid" = ""RTL5682""
215 register "name" = ""RT58""
216 register "desc" = ""Realtek RT5682""
217 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
218 register "property_count" = "1"
219 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
220 register "property_list[0].name" = ""realtek,jd-src""
221 register "property_list[0].integer" = "1"
222 device i2c 1a on
223 probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
224 end
225 end
226 end # I2C 4
227 device pci 1c.2 on
228 chip drivers/net
229 register "customized_leds" = "0x07af"
230 register "wake" = "GPE0_DW0_03" # GPP_B3
231 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
232 register "device_index" = "0"
233 device pci 00.0 on end
234 end
235 end # PCI Express Root Port 3 - RTL8111H LAN
236 device pci 1c.6 on
237 chip drivers/wifi/generic
238 register "wake" = "GPE0_DW2_03"
239 device pci 00.0 on end
240 end
241 end # PCI Express Root Port 7 - WLAN
242 device pci 1c.7 off end # PCI Express Root Port 8
243 device pci 1f.3 on end # Intel HDA
244 end
245 end
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