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soc/intel/ptl: Update ME specification version to 21
[coreboot.git] / src / mainboard / google / eve / devicetree.cb
blobc0779c664ba4ae9ad65f8633e2fe38c5acb372dd
1 chip soc/intel/skylake
2
3 # IGD Displays
4 register "gfx" = "GMA_STATIC_DISPLAYS(0)"
5
6 register "panel_cfg" = "{
7 .up_delay_ms = 100,
8 .down_delay_ms = 500,
9 .cycle_delay_ms = 500,
10 .backlight_on_delay_ms = 1,
11 .backlight_off_delay_ms = 200,
12 .backlight_pwm_hz = 1000,
13 }"
14
15 # Enable deep Sx states
16 register "deep_s3_enable_ac" = "0"
17 register "deep_s3_enable_dc" = "1"
18 register "deep_s5_enable_ac" = "1"
19 register "deep_s5_enable_dc" = "1"
20 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
21
22 register "eist_enable" = "true"
23
24 # GPE configuration
25 # Note that GPE events called out in ASL code rely on this
26 # route. i.e. If this route changes then the affected GPE
27 # offset bits also need to be changed.
28 register "gpe0_dw0" = "GPP_B"
29 register "gpe0_dw1" = "GPP_D"
30 register "gpe0_dw2" = "GPP_E"
31
32 # FSP Configuration
33 register "DspEnable" = "1"
34 register "IoBufferOwnership" = "3"
35 register "ScsEmmcHs400Enabled" = "1"
36 register "SkipExtGfxScan" = "1"
37 register "SaGv" = "SaGv_Enabled"
38 register "PmConfigSlpS3MinAssert" = "2" # 50ms
39 register "PmConfigSlpS4MinAssert" = "1" # 1s
40 register "PmConfigSlpSusMinAssert" = "1" # 500ms
41 register "PmConfigSlpAMinAssert" = "3" # 2s
42
43 # VR Settings Configuration for 4 Domains
44 #+----------------+-------+-------+-------+-------+
45 #| Domain/Setting | SA | IA | GTUS | GTS |
46 #+----------------+-------+-------+-------+-------+
47 #| Psi1Threshold | 20A | 20A | 20A | 20A |
48 #| Psi2Threshold | 2A | 2A | 2A | 2A |
49 #| Psi3Threshold | 1A | 1A | 1A | 1A |
50 #| Psi3Enable | 1 | 1 | 1 | 1 |
51 #| Psi4Enable | 1 | 1 | 1 | 1 |
52 #| ImonSlope | 0 | 0 | 0 | 0 |
53 #| ImonOffset | 0 | 0 | 0 | 0 |
54 #| IccMax | 4A | 24A | 24A | 24A |
55 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
56 #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 |
57 #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 |
58 #+----------------+-------+-------+-------+-------+
59 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
60 .vr_config_enable = 1,
61 .psi1threshold = VR_CFG_AMP(20),
62 .psi2threshold = VR_CFG_AMP(2),
63 .psi3threshold = VR_CFG_AMP(1),
64 .psi3enable = 1,
65 .psi4enable = 1,
66 .imon_slope = 0x0,
67 .imon_offset = 0x0,
68 .icc_max = VR_CFG_AMP(4),
69 .voltage_limit = 1520,
70 .ac_loadline = 1490,
71 .dc_loadline = 1420,
72 }"
73
74 register "domain_vr_config[VR_IA_CORE]" = "{
75 .vr_config_enable = 1,
76 .psi1threshold = VR_CFG_AMP(20),
77 .psi2threshold = VR_CFG_AMP(2),
78 .psi3threshold = VR_CFG_AMP(1),
79 .psi3enable = 1,
80 .psi4enable = 1,
81 .imon_slope = 0x0,
82 .imon_offset = 0x0,
83 .icc_max = VR_CFG_AMP(24),
84 .voltage_limit = 1520,
85 .ac_loadline = 500,
86 .dc_loadline = 486,
87 }"
88
89 register "domain_vr_config[VR_GT_UNSLICED]" = "{
90 .vr_config_enable = 1,
91 .psi1threshold = VR_CFG_AMP(20),
92 .psi2threshold = VR_CFG_AMP(2),
93 .psi3threshold = VR_CFG_AMP(1),
94 .psi3enable = 1,
95 .psi4enable = 1,
96 .imon_slope = 0x0,
97 .imon_offset = 0x0,
98 .icc_max = VR_CFG_AMP(24),
99 .voltage_limit = 1520,
100 .ac_loadline = 570,
101 .dc_loadline = 420,
102 }"
103
104 register "domain_vr_config[VR_GT_SLICED]" = "{
105 .vr_config_enable = 1,
106 .psi1threshold = VR_CFG_AMP(20),
107 .psi2threshold = VR_CFG_AMP(2),
108 .psi3threshold = VR_CFG_AMP(1),
109 .psi3enable = 1,
110 .psi4enable = 1,
111 .imon_slope = 0x0,
112 .imon_offset = 0x0,
113 .icc_max = VR_CFG_AMP(24),
114 .voltage_limit = 1520,
115 .ac_loadline = 457,
116 .dc_loadline = 430,
117 }"
118
119 # Intel Common SoC Config
120 #+-------------------+---------------------------+
121 #| Field | Value |
122 #+-------------------+---------------------------+
123 #| I2C0 | Touchscreen |
124 #| I2C1 | Early TPM access |
125 #| I2C2 | Touchpad |
126 #| I2C4 | Audio |
127 #+-------------------+---------------------------+
128 register "common_soc_config" = "{
129 .i2c[0] = {
130 .speed = I2C_SPEED_FAST_PLUS,
131 .rise_time_ns = 98,
132 .fall_time_ns = 38,
133 },
134 .i2c[1] = {
135 .early_init = 1,
136 .speed = I2C_SPEED_FAST,
137 .rise_time_ns = 112,
138 .fall_time_ns = 34,
139 },
140 .i2c[2] = {
141 .speed = I2C_SPEED_FAST,
142 .speed_config[0] = {
143 .speed = I2C_SPEED_FAST,
144 .scl_lcnt = 186,
145 .scl_hcnt = 93,
146 .sda_hold = 36,
147 }
148 },
149 .i2c[4] = {
150 .speed = I2C_SPEED_FAST,
151 .speed_config[0] = {
152 .speed = I2C_SPEED_FAST,
153 .scl_lcnt = 176,
154 .scl_hcnt = 95,
155 .sda_hold = 36,
156 }
157 },
158 }"
159
160 # Touchscreen
161 register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
162
163 # Enable I2C1 bus early for TPM access
164 register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
165
166 # Touchpad
167 register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
168
169 # Audio
170 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
171
172 # Must leave UART0 enabled or SD/eMMC will not work as PCI
173 register "SerialIoDevMode" = "{
174 [PchSerialIoIndexI2C0] = PchSerialIoPci,
175 [PchSerialIoIndexI2C1] = PchSerialIoPci,
176 [PchSerialIoIndexI2C2] = PchSerialIoPci,
177 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
178 [PchSerialIoIndexI2C4] = PchSerialIoPci,
179 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
180 [PchSerialIoIndexSpi0] = PchSerialIoPci,
181 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
182 [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
183 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
184 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
185 }"
186
187 register "dptf_enable" = "1"
188 register "power_limits_config" = "{
189 .tdp_pl1_override = 7,
190 .tdp_pl2_override = 15,
191 }"
192 register "tcc_offset" = "10"
193
194 device domain 0 on
195 device ref igpu on end
196 device ref sa_thermal on end
197 device ref south_xhci on
198 register "usb2_ports" = "{
199 [0] = USB2_PORT_LONG(OC0), // Type-C Port 1
200 [1] = USB2_PORT_FLEX(OC_SKIP), // Camera
201 [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
202 [4] = USB2_PORT_LONG(OC1), // Type-C Port 2
203 [6] = USB2_PORT_MID(OC_SKIP), // H1
204 }"
205
206 register "usb3_ports" = "{
207 [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
208 [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
209 }"
210 chip drivers/usb/acpi
211 register "desc" = ""Root Hub""
212 register "type" = "UPC_TYPE_HUB"
213 device usb 0.0 on
214 chip drivers/usb/acpi
215 register "desc" = ""USB2 Type-C Left""
216 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
217 register "group" = "ACPI_PLD_GROUP(1, 1)"
218 device usb 2.0 on end
219 end
220 chip drivers/usb/acpi
221 register "desc" = ""USB2 Camera""
222 register "type" = "UPC_TYPE_INTERNAL"
223 device usb 2.1 on end
224 end
225 chip drivers/usb/acpi
226 register "desc" = ""USB2 Bluetooth""
227 register "type" = "UPC_TYPE_INTERNAL"
228 device usb 2.2 on end
229 end
230 chip drivers/usb/acpi
231 register "desc" = ""USB2 Type-C Right""
232 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
233 register "group" = "ACPI_PLD_GROUP(2, 1)"
234 device usb 2.4 on end
235 end
236 chip drivers/usb/acpi
237 register "desc" = ""USB2 H1 TPM""
238 register "type" = "UPC_TYPE_INTERNAL"
239 device usb 2.6 on end
240 end
241 chip drivers/usb/acpi
242 register "desc" = ""USB3 Type-C Left""
243 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
244 register "group" = "ACPI_PLD_GROUP(1, 1)"
245 device usb 3.0 on end
246 end
247 chip drivers/usb/acpi
248 register "desc" = ""USB3 Type-C Right""
249 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
250 register "group" = "ACPI_PLD_GROUP(2, 1)"
251 device usb 3.1 on end
252 end
253 end
254 end
255 end
256 device ref thermal on end
257 device ref i2c0 on
258 chip drivers/i2c/hid
259 register "generic.hid" = ""WCOM50C1""
260 register "generic.desc" = ""WCOM Digitizer""
261 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
262 register "generic.speed" = "I2C_SPEED_FAST_PLUS"
263 register "hid_desc_reg_offset" = "0x1"
264 device i2c 0a on end
265 end
266 end
267 device ref i2c1 on
268 chip drivers/i2c/tpm
269 register "hid" = ""GOOG0005""
270 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
271 device i2c 50 on end
272 end
273 end
274 device ref i2c2 on
275 chip drivers/i2c/hid
276 register "generic.hid" = ""ACPI0C50""
277 register "generic.sub" = ""1AE0006B""
278 register "generic.desc" = ""Touchpad""
279 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
280 register "hid_desc_reg_offset" = "0x1"
281 device i2c 49 on end
282 end
283 chip drivers/i2c/generic
284 register "hid" = ""GOOG0008""
285 register "desc" = ""Touchpad EC Interface""
286 device i2c 1e on end
287 end
288 end
289 device ref heci1 on end
290 device ref uart2 on end
291 device ref i2c4 on
292 chip drivers/i2c/max98927
293 register "interleave_mode" = "1"
294 register "vmon_slot_no" = "4"
295 register "imon_slot_no" = "5"
296 register "uid" = "0"
297 register "desc" = ""Right Speaker Amp""
298 register "name" = ""MAXR""
299 device i2c 39 on end
300 end
301 chip drivers/i2c/max98927
302 register "interleave_mode" = "1"
303 register "vmon_slot_no" = "6"
304 register "imon_slot_no" = "7"
305 register "uid" = "1"
306 register "desc" = ""Left Speaker Amp""
307 register "name" = ""MAXL""
308 device i2c 3a on end
309 end
310 chip drivers/i2c/rt5663
311 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH_WAKE(GPP_D9)"
312 register "dc_offset_l_manual" = "0xffd160"
313 register "dc_offset_r_manual" = "0xffd1c0"
314 register "dc_offset_l_manual_mic" = "0xff8a10"
315 register "dc_offset_r_manual_mic" = "0xff8ab0"
316 device i2c 13 on end
317 end
318 chip drivers/i2c/generic
319 register "hid" = ""10EC5514""
320 register "name" = ""RT54""
321 register "desc" = ""Realtek RT5514""
322 register "property_count" = "3"
323 # Set the DMIC initial delay to 16ms to avoid pop noise
324 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
325 register "property_list[0].name" = ""realtek,dmic-init-delay""
326 register "property_list[0].integer" = "16"
327 # Set clock name for RT5514 to calibrate DSP clock.
328 register "property_list[1].type" = "ACPI_DP_TYPE_STRING"
329 register "property_list[1].name" = ""realtek,dsp-calib-clk-name""
330 register "property_list[1].string" = ""ssp1_mclk""
331 # Set clock rate for RT5514 to calibrate DSP clock.
332 register "property_list[2].type" = "ACPI_DP_TYPE_INTEGER"
333 register "property_list[2].name" = ""realtek,dsp-calib-clk-rate""
334 register "property_list[2].integer" = "24000000"
335 device i2c 57 on end
336 end
337 end # I2C #4
338 device ref pcie_rp1 on
339 register "PcieRpEnable[0]" = "1"
340 register "PcieRpClkReqSupport[0]" = "1"
341 register "PcieRpClkReqNumber[0]" = "1"
342 register "PcieRpAdvancedErrorReporting[0]" = "1"
343 register "PcieRpLtrEnable[0]" = "1"
344 register "PcieRpHotPlug[0]" = "1"
345 register "PcieRpClkSrcNumber[0]" = "1"
346 chip drivers/wifi/generic
347 register "wake" = "GPE0_PCI_EXP"
348 device pci 00.0 on end
349 end
350 end
351 device ref pcie_rp5 on
352 register "PcieRpEnable[4]" = "1"
353 register "PcieRpClkReqSupport[4]" = "1"
354 register "PcieRpClkReqNumber[4]" = "4"
355 register "PcieRpAdvancedErrorReporting[4]" = "1"
356 register "PcieRpLtrEnable[4]" = "1"
357 register "PcieRpClkSrcNumber[4]" = "4"
358 end
359 device ref uart0 on end
360 device ref gspi0 on
361 chip drivers/spi/acpi
362 register "hid" = "ACPI_DT_NAMESPACE_HID"
363 register "compat_string" = ""realtek,rt5514""
364 register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F10_IRQ)"
365 register "speed" = "12 * MHz"
366 device spi 0 on end
367 end
368 end
369 device ref emmc on end
370 device ref lpc_espi on
371 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
372 register "gen1_dec" = "0x00fc0801"
373 register "gen2_dec" = "0x000c0201"
374 # EC memory map range is 0x900-0x9ff
375 register "gen3_dec" = "0x00fc0901"
376
377 chip ec/google/chromeec
378 device pnp 0c09.0 on end
379 end
380 end
381 device ref hda on end
382 device ref smbus on end
383 device ref fast_spi on end
384 end
385 end
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