src/mainboard/google/fatcat/variants/felino/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <boardid.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage*/
   9 static const struct pad_config gpio_table[] = {
  10         /* GPP_A00:     ESPI_IO0_EC_R */
  11         /*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
  12
  13         /* GPP_A01:     ESPI_IO1_EC_R */
  14         /*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
  15
  16         /* GPP_A02:     ESPI_IO2_EC_R */
  17         /*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
  18
  19         /* GPP_A03:     ESPI_IO3_EC_R */
  20         /*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
  21
  22         /* GPP_A04:     ESPI_CS0_EC_R_N */
  23         /*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
  24
  25         /* GPP_A05:     ESPI_CLK_EC_R */
  26         /*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
  27
  28         /* GPP_A06:     ESPI_RST_EC_R_N */
  29         /*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
  30
  31         /* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
  32         PAD_CFG_GPO(GPP_A08, 1, PLTRST),
  33         /* GPP_A09:     M.2_WWAN_FCP_OFF_N */
  34         PAD_CFG_GPO(GPP_A09, 1, PLTRST),
  35         /* GPP_A10:     M.2_WWAN_DISABLE_N */
  36         PAD_CFG_GPO(GPP_A10, 1, PLTRST),
  37         /* GPP_A11:     WLAN_RST_N */
  38         PAD_CFG_GPO(GPP_A11, 1, PLTRST),
  39         /* GPP_A12:     WIFI_WAKE_N */
  40         PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
  41         /* GPP_A13:     Not used */
  42         PAD_NC(GPP_A13, NONE),
  43         /* GPP_A15:     GPP_A15_DNX_FORCE_RELOAD */
  44         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  45         /* GPP_A16:     BT_RF_KILL_N */
  46         PAD_CFG_GPO(GPP_A16, 1, DEEP),
  47         /* GPP_A17:     WIFI_RF_KILL_N */
  48         PAD_CFG_GPO(GPP_A17, 1, DEEP),
  49
  50         /* GPP_B00:     USBC_SML_CLK_PD */
  51         PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
  52         /* GPP_B01:     USBC_SML_DATA_PD */
  53         PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
  54         /* GPP_B02:     ISH_I2C0_SDA_SNSR_HDR */
  55         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
  56         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
  57         /* GPP_B03:     ISH_I2C0_SCL_SNSR_HDR */
  58         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
  59         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
  60         /* GPP_B04:     ISH_GP_0_SNSR_HDR */
  61         PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
  62         /* GPP_B05:     ISH_GP_1_SNSR_HDR */
  63         PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
  64         /* GPP_B06:     ISH_GP_2_SNSR_HDR */
  65         PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
  66         /* GPP_B07:     ISH_GP_3_SNSR_HDR */
  67         PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
  68         /* GPP_B08:     ISH_GP_4_SNSR_HDR */
  69         PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
  70         /* GPP_B09:     M2_GEN4_SSD_RESET_N */
  71         PAD_CFG_GPO(GPP_B09, 1, PLTRST),
  72         /* GPP_B10:     GEN4_SSD_PWREN */
  73         PAD_CFG_GPO(GPP_B10, 1, PLTRST),
  74         /* GPP_B11:     MOD_TCSS1_DISP_HPD3 */
  75         PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
  76         /* GPP_B12:     PM_SLP_S0_N */
  77         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  78         /* GPP_B13:     PLT_RST_N */
  79         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  80         /* GPP_B14:     MOD_TCSS2_DISP_HPD4 */
  81         PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
  82         /* GPP_B15:     MOD_TCSS_USB_TYP_A_OC3_N */
  83         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  84         /* GPP_B16:     GEN5_SSD_PWREN */
  85         PAD_CFG_GPO(GPP_B16, 1, PLTRST),
  86         /* GPP_B17:     Not used */
  87         PAD_NC(GPP_B17, NONE),
  88         /* GPP_B18:     ISH_I2C2_SDA_SNSR_HDR */
  89         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
  90         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
  91         /* GPP_B19:     ISH_I2C2_SCL_SNSR_HDR */
  92         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
  93         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
  94         /* GPP_B20:     M.2_WWAN_RST_N */
  95         PAD_CFG_GPO(GPP_B20, 1, PLTRST),
  96         /* GPP_B21:     TCP_RETIMER_FORCE_PWR */
  97         PAD_CFG_GPO(GPP_B21, 0, DEEP),
  98         /* GPP_B22:     ISH_GP_5_SNSR_HDR */
  99         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
 100         /* GPP_B23:     ISH_GP_6_SNSR_HDR */
 101         PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
 102         /* GPP_B24:     ESPI_ALERT0_EC_R_N */
 103         PAD_NC(GPP_B24, NONE),
 104         /* GPP_B25:     X1_SLOT_WAKE_N */
 105         PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
 106
 107         /* GPP_C00:     GPP_C0_SMBCLK */
 108         PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 109         /* GPP_C01:     GPP_C1_SMBDATA */
 110         PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 111         /* GPP_C02:     Not used */
 112         PAD_NC(GPP_C02, NONE),
 113         /* GPP_C03:     TCP_LAN_SML0_SCL_R */
 114         PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
 115         /* GPP_C04:     TCP_LAN_SML0_SDA_R */
 116         PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
 117         /* GPP_C05:     CRD1_PWREN */
 118         PAD_CFG_GPO(GPP_C05, 1, PLTRST),
 119         /* GPP_C06:     SML1_CLK */
 120         PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
 121         /* GPP_C07:     SML1_DATA */
 122         PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
 123         /* GPP_C08:     CRD2_PWREN */
 124         PAD_CFG_GPO(GPP_C08, 1, PLTRST),
 125         /* GPP_C09:     CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
 126         PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
 127         /* GPP_C10:     CLKREQ1_X4_GEN5_M2_SSD_N */
 128         PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
 129         /* GPP_C11:     CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
 130         PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
 131         /* GPP_C12:     CLKREQ3_X1_GEN1_GBE_LAN_N */
 132         PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
 133         /* GPP_C13:     CLKREQ4_X1_GEN4_M2_WLAN_N */
 134         PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 135         /* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
 136         PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 137         /* GPP_C15:     CRD1_CLK_EN */
 138         PAD_CFG_GPO(GPP_C15, 1, PLTRST),
 139         /* GPP_C16:     TBT_LSX0_TXD  */
 140         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 141         /* GPP_C17:     TBT_LSX0_RXD  */
 142         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 143         /* GPP_C18:     TBT_LSX1_TXD  */
 144         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 145         /* GPP_C19:     TBT_LSX1_RXD */
 146         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 147         /* GPP_C20:     MOD_TCSS1_LS_TX_DDC_SCL */
 148         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 149         /* GPP_C21:     MOD_TCSS1_LS_RX_DDC_SDA */
 150         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 151         /* GPP_C22:     MOD_TCSS2_LS_TX_DDC_SCL */
 152         PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
 153         /* GPP_C23:     MOD_TCSS2_LS_RX_DDC_SDA */
 154         PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
 155
 156         /* GPP_D00:     IMGCLKOUT_1 */
 157         PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
 158         /* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
 159         PAD_CFG_GPO(GPP_D01, 1, DEEP),
 160         /* GPP_D02:     Not used */
 161         PAD_NC(GPP_D02, NONE),
 162         /* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
 163         PAD_CFG_GPO(GPP_D03, 1, PLTRST),
 164         /* GPP_D04:     IMGCLKOUT_0 */
 165         PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
 166         /* GPP_D07:     NC */
 167         PAD_NC(GPP_D07, NONE),
 168         /* GPP_D08:     NC */
 169         PAD_NC(GPP_D08, NONE),
 170         /* GPP_D09:     PEG_SLOT_RST_N */
 171         PAD_CFG_GPO(GPP_D09, 1, PLTRST),
 172         /* GPP_D10:     HDA_BCLK */
 173         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
 174         /* GPP_D11:     HDA_SYNC */
 175         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
 176         /* GPP_D12:     HDA_SDO */
 177         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
 178         /* GPP_D13:     HDA_SDI0 */
 179         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
 180         /* GPP_D14:     COINLESS_MODE_SELECT */
 181         PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
 182         /* GPP_D15:     SPI_TPM_INT_N */
 183         PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
 184         /* GPP_D16:     HDA_RST_N_HDR */
 185         PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
 186         /* GPP_D17:     HDA_SDI1_HDR */
 187         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 188         /* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
 189         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 190         /* GPP_D19:     X1_DT_PCIE_RST_N */
 191         PAD_CFG_GPO(GPP_D19, 1, PLTRST),
 192         /* GPP_D20:     CSE_EARLY_SW */
 193         PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
 194         /* GPP_D21:     GPP_D21_UFS_REFCLK */
 195         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 196         /* GPP_D22:     BPKI3C_SDA */
 197         PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 198         /* GPP_D23:     BPKI3C_SCL */
 199         PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 200         /* GPP_D24:     PEG_SLOT_WAKE_N */
 201         PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
 202         /* GPP_D25:     X4_SLOT_WAKE_N */
 203         PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
 204
 205         /* GPP_E01:     CRD2_RST_N */
 206         PAD_CFG_GPO(GPP_E01, 1, PLTRST),
 207         /* GPP_E02:     WWAN_WAKE_GPIO_N  */
 208         PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
 209         /* GPP_E03:     M2_GEN5_SSD_RESET_N */
 210         PAD_CFG_GPO(GPP_E03, 1, PLTRST),
 211         /* GPP_E06:     SECURE_CAM_SW */
 212         PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
 213         /* GPP_E07:     Not used */
 214         PAD_NC(GPP_E07, NONE),
 215         /* GPP_E08:     Not used */
 216         PAD_NC(GPP_E08, NONE),
 217         /* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */
 218         PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
 219         /* GPP_E10:     CRD1_RST_N */
 220         PAD_CFG_GPO(GPP_E10, 1, PLTRST),
 221         /* GPP_E11:     THC0_SPI1_CLK_TCH_PNL1 */
 222         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
 223         /* GPP_E12:     THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
 224         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
 225         /* GPP_E13:     THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
 226         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
 227         /* GPP_E14:     THC0_SPI1_IO_2_TCH_PNL1 */
 228         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
 229         /* GPP_E15:     THC0_SPI1_IO_3_TCH_PNL1 */
 230         PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
 231         /* GPP_E16:     THC0_SPI1_RST_N_TCH_PNL1 */
 232         /* THC NOTE: use GPO instead of GPO for THC0 Rst */
 233         PAD_CFG_GPO(GPP_E16, 1, DEEP),
 234         /* GPP_E17:     THC0_SPI1_CS0_N_TCH_PNL1 */
 235         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
 236         /* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
 237         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 238         /* GPP_E19:     PEG_SLOT_DGPU_SEL_N */
 239         PAD_CFG_GPO(GPP_E19, 1, PLTRST),
 240         /* GPP_E20:     PEG_SLOT_DGPU_PWR_OK */
 241         PAD_CFG_GPI(GPP_E20, NONE, PLTRST),
 242         /* GPP_E21:     I2C_PMC_PD_INT_N */
 243         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 244         /* GPP_E22:     THC0_SPI1_DSYNC */
 245         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
 246
 247         /* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 248         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 249         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
 250         /* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
 251         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 252         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
 253         /* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
 254         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 255         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
 256         /* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
 257         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 258         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
 259         /* GPP_F04:     CNV_RF_RESET_R_N */
 260         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 261         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 262         /* GPP_F05:     CRF_CLKREQ_R */
 263         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 264         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
 265         /* GPP_F06:     WLAN_WWAN_COEX3 */
 266         PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
 267         /* GPP_F07:     IMGCLKOUT_2 */
 268         PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
 269         /* GPP_F08:     TCH_PNL1_PWR_EN */
 270         PAD_CFG_GPO(GPP_F08, 1, PLTRST),
 271         /* GPP_F09:     NC */
 272         PAD_NC(GPP_F09, NONE),
 273         /* GPP_F10:     PEG_SLOT_PWR_EN_N */
 274         PAD_CFG_GPO(GPP_F10, 0, PLTRST),
 275         /* GPP_F11:     MOD_TCSS2_TYP_A_VBUS_EN */
 276         PAD_CFG_GPO(GPP_F11, 1, DEEP),
 277         /* GPP_F12:     THC_I2C1_SCL_TCH_PAD */
 278         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
 279         /* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
 280         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 281         /* GPP_F14:     Not used */
 282         PAD_NC(GPP_F14, NONE),
 283         /* GPP_F15:     Not used */
 284         PAD_NC(GPP_F15, NONE),
 285         /* GPP_F16:     Not used */
 286         PAD_NC(GPP_F16, NONE),
 287         /* GPP_F17:     Not used */
 288         PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
 289         /* GPP_F18:     TCH_PAD_INT_N */
 290         PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
 291         /* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
 292         PAD_CFG_GPO(GPP_F19, 0, PLTRST),
 293         /* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
 294         PAD_CFG_GPO(GPP_F20, 0, PLTRST),
 295         /* GPP_F22:     THC1_SPI2_DSYNC */
 296         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
 297         /* GPP_F23:     SMC_LID */
 298         PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL),
 299
 300         /* GPP_H00:     Not used */
 301         PAD_NC(GPP_H00, NONE),
 302         /* GPP_H01:     CRD_CAM_STROBE */
 303         PAD_CFG_GPO(GPP_H01, 0, PLTRST),
 304         /* GPP_H02:     DEBUG_TRACE_PNP */
 305         PAD_CFG_GPO(GPP_H02, 1, PLTRST),
 306         /* GPP_H03:     MIC MUTE */
 307         PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
 308         /* GPP_H04:     I2C2_SDA_CAM_FLSH */
 309         PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
 310         /* GPP_H05:     I2C2_SCL_CAM_FLSH */
 311         PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
 312         /* GPP_H06:     I2C3_SDA_PSS */
 313         PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 314         /* GPP_H07:     I2C3_SCL_PSS */
 315         PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 316         /* GPP_H08:     UART0_BUF_RXD */
 317         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 318         /* GPP_H09:     UART0_BUF_TXD */
 319         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 320         /* GPP_H10:     UART0_BUF_RTS */
 321         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
 322         /* GPP_H11:     UART0_BUF_CTS */
 323         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
 324         /* GPP_H13:     CPU_C10_GATE_N_R */
 325         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 326         /* GPP_H14:     NC */
 327         PAD_NC(GPP_H14, NONE),
 328         /* GPP_H15:     NC */
 329         PAD_NC(GPP_H15, NONE),
 330         /* GPP_H16:     WWAN_PWREN */
 331         PAD_CFG_GPO(GPP_H16, 1, PLTRST),
 332         /* GPP_H17:     MIC MUTE LED */
 333         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 334         /* GPP_H19:     I3C0_SDA_HDR */
 335         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
 336         /* GPP_H20:     I3C0_SCL_HDR */
 337         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
 338         /* GPP_H21:     I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
 339         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 340         /* GPP_H22:     I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
 341         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 342
 343         /* GPP_S00:     SNDW3_CLK_CODEC */
 344         PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
 345         /* GPP_S01:     SNDW3_DATA0_CODEC */
 346         PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
 347         /* GPP_S02:     SNDW3_DATA1_CODEC */
 348         PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
 349         /* GPP_S03:     SNDW3_DATA2_CODEC */
 350         PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
 351         /* GPP_S04:     SNDW2_CLK */
 352         PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
 353         /* GPP_S05:     SNDW2_DATA0 */
 354         PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
 355         /* GPP_S06:     SNDW1_CLK */
 356         PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
 357         /* GPP_S07:     SNDW1_DATA0 */
 358         PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
 359
 360         /* GPP_V00:     PM_BATLOW_N */
 361         PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 362         /* GPP_V01:     BC_ACOK_MCP */
 363         PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
 364         /* GPP_V02:     LANWAKE_N_R */
 365         PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 366         /* GPP_V03:     PWRBTN_MCP_N */
 367         PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 368         /* GPP_V04:     PM_SLP_S3_N */
 369         PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 370         /* GPP_V05:     PM_SLP_S4_N */
 371         PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 372         /* GPP_V06:     PM_SLP_A_N */
 373         PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
 374         /* GPP_V07:     Not used */
 375         PAD_NC(GPP_V07, NONE),
 376         /* GPP_V08:     SLP_WLAN_N */
 377         PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 378         /* GPP_V09:     PM_SLP_S5_N */
 379         PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
 380         /* GPP_V10:     LANPHYPC_R_N */
 381         PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
 382         /* GPP_V11:     PM_SLP_LAN_N */
 383         PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
 384         /* GPP_V12:     WAKE_N */
 385         PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 386         /* GPP_V13:     GPP_V13_CATERR_N */
 387         PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
 388         /* GPP_V14:     GPP_V14_FORCEPR_N */
 389         PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
 390         /* GPP_V15:     GPP_V15_THERMTRIP_N */
 391         PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
 392         /* GPP_V16:     GPP_V16_VCCST_EN */
 393         PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
 394         /* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
 395         PAD_CFG_GPO(GPP_V17, 1, DEEP),
 396 };
 397
 398 /* Early pad configuration in bootblock */
 399 static const struct pad_config early_gpio_table[] = {
 400         /* GPP_H08:     UART0_BUF_RXD */
 401         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 402         /* GPP_H09:     UART0_BUF_TXD */
 403         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 404
 405         /* GPP_H06: I2C3_SDA_PSS */
 406         PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 407         /* GPP_H07: I2C3_SCL_PSS */
 408         PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 409         /* GPP_D15: SPI_TPM_INT_N */
 410         PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
 411 };
 412
 413 /* Pad configuration in romstage */
 414 static const struct pad_config romstage_gpio_table[] = {
 415         /* GPP_C00:     GPP_C0_SMBCLK */
 416         PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 417         /* GPP_C01:     GPP_C1_SMBDATA */
 418         PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 419 };
 420
 421 const struct pad_config *variant_gpio_table(size_t *num)
 422 {
 423         *num = ARRAY_SIZE(gpio_table);
 424         return gpio_table;
 425 }
 426
 427 const struct pad_config *variant_early_gpio_table(size_t *num)
 428 {
 429         *num = ARRAY_SIZE(early_gpio_table);
 430         return early_gpio_table;
 431 }
 432
 433 /* Create the stub for romstage gpio, typically use for power sequence */
 434 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 435 {
 436         *num = ARRAY_SIZE(romstage_gpio_table);
 437         return romstage_gpio_table;
 438 }
 439
 440 static const struct cros_gpio cros_gpios[] = {
 441         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
 442         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 443         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 444         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
 445 };
 446
 447 DECLARE_CROS_GPIOS(cros_gpios);