src/mainboard/google/gru/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <bootblock_common.h>
   5 #include <delay.h>
   6 #include <soc/grf.h>
   7 #include <gpio.h>
   8 #include <soc/clock.h>
   9 #include <soc/i2c.h>
  10 #include <soc/pwm.h>
  11 #include <soc/spi.h>
  12 #include <vendorcode/google/chromeos/chromeos.h>
  13
  14 #include "board.h"
  15 #include "pwm_regulator.h"
  16
  17 void bootblock_mainboard_early_init(void)
  18 {
  19         /* Configure all programmable IO voltage domains (3D/4A and 2A/2B) early
  20            so that we know we can use our GPIOs reliably in following code. */
  21         write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1 | 1 << 0));
  22         /* On Scarlet-based boards, the 4C/4D domain is 1.8V (on others 3.0V) */
  23         if (CONFIG(GRU_BASEBOARD_SCARLET))
  24                 write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3));
  25
  26         /* Reconfigure GPIO1 from dynamic voltage selection through GPIO0_B1 to
  27            hardcoded 1.8V, and change that pin to a normal GPIO. The TRM says
  28            this is already the power-on reset, but we all know that TRMs lie. */
  29         write32(&rk3399_pmugrf->soc_con0, RK_SETBITS(1 << 9 | 1 << 8));
  30         write32(&rk3399_pmugrf->gpio0b_iomux, RK_CLRBITS(3 << 2));
  31
  32         /* Enable rails powering GPIO blocks, among other things. */
  33         gpio_output(GPIO_P30V_EN, 1);
  34         if (!CONFIG(GRU_BASEBOARD_SCARLET))
  35                 gpio_output(GPIO_P15V_EN, 1);   /* Scarlet: EC-controlled */
  36
  37         if (CONFIG(CONSOLE_SERIAL)) {
  38                 _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
  39                                "CONSOLE_SERIAL_UART should be UART2");
  40
  41                 /* iomux: select gpio4c[4:3] as uart2 dbg port */
  42                 write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
  43
  44                 /* grf soc_con7[11:10] use for uart2 select */
  45                 write32(&rk3399_grf->soc_con7, UART2C_SEL);
  46         }
  47 }
  48
  49 static void configure_spi_flash(void)
  50 {
  51         gpio_input(GPIO(1, A, 7));      /* SPI1_MISO remove pull-up */
  52         gpio_input(GPIO(1, B, 0));      /* SPI1_MOSI remove pull-up */
  53         gpio_input(GPIO(1, B, 1));      /* SPI1_CLK remove pull-up */
  54         gpio_input(GPIO(1, B, 2));      /* SPI1_CS remove pull-up */
  55
  56         rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33*MHz);
  57         rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5);
  58
  59         write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
  60         write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
  61 }
  62
  63 static void configure_ec(void)
  64 {
  65         gpio_input(GPIO(2, C, 4));      /* SPI5_MISO remove pull-up */
  66         gpio_input(GPIO(2, C, 5));      /* SPI5_MOSI remove pull-up */
  67         gpio_input(GPIO(2, C, 6));      /* SPI5_CLK remove pull-up */
  68         gpio_input_pullup(GPIO(2, C, 7));       /* SPI5_CS confirm pull-up */
  69
  70         rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
  71
  72         write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);
  73 }
  74
  75 static void configure_tpm(void)
  76 {
  77         if (CONFIG(GRU_HAS_TPM2)) {
  78                 rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
  79
  80                 if (CONFIG(GRU_BASEBOARD_SCARLET)) {
  81                         gpio_input(GPIO(2, B, 1));      /* SPI2_MISO no-pull */
  82                         gpio_input(GPIO(2, B, 2));      /* SPI2_MOSI no-pull */
  83                         gpio_input(GPIO(2, B, 3));      /* SPI2_CLK no-pull */
  84                         gpio_input_pullup(GPIO(2, B, 4));       /* SPI2_CS */
  85                         write32(&rk3399_grf->iomux_spi2, IOMUX_SPI2);
  86                 } else {
  87                         gpio_input(GPIO(3, A, 4));      /* SPI0_MISO no-pull */
  88                         gpio_input(GPIO(3, A, 5));      /* SPI0_MOSI no-pull */
  89                         gpio_input(GPIO(3, A, 6));      /* SPI0_CLK no-pull */
  90                         gpio_input_pullup(GPIO(3, A, 7));       /* SPI0_CS */
  91                         write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
  92                 }
  93
  94                 gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING, GPIO_PULLUP);
  95         } else {
  96                 gpio_input(GPIO(1, B, 7));      /* I2C0_SDA remove pull-up */
  97                 gpio_input(GPIO(1, C, 0));      /* I2C0_SCL remove pull-up */
  98
  99                 i2c_init(0, 400*KHz);
 100
 101                 write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
 102                 write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
 103         }
 104 }
 105
 106 static void speed_up_boot_cpu(void)
 107 {
 108         pwm_regulator_configure(PWM_REGULATOR_LIT, 1150);
 109
 110         udelay(200);
 111
 112         rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE);
 113 }
 114
 115 void bootblock_mainboard_init(void)
 116 {
 117         speed_up_boot_cpu();
 118
 119         if (rkclk_was_watchdog_reset())
 120                 reboot_from_watchdog();
 121
 122         configure_spi_flash();
 123         configure_ec();
 124         configure_tpm();
 125
 126         setup_chromeos_gpios();
 127 }