src/mainboard/google/guybrush/port_descriptors.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <device/device.h>
   5 #include <device/pci_def.h>
   6 #include <gpio.h>
   7 #include <soc/platform_descriptors.h>
   8 #include <static.h>
   9 #include <types.h>
  10
  11 /* All PCIe Resets are handled in coreboot */
  12 static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
  13         { /* WLAN */
  14                 .engine_type = PCIE_ENGINE,
  15                 .port_present = true,
  16                 .start_logical_lane = 0,
  17                 .end_logical_lane = 0,
  18                 .link_speed_capability = GEN3,
  19                 .device_number = PCI_SLOT(WLAN_DEVFN),
  20                 .function_number = PCI_FUNC(WLAN_DEVFN),
  21                 .link_aspm = ASPM_L1,
  22                 .link_aspm_L1_1 = false,
  23                 .link_aspm_L1_2 = false,
  24                 .turn_off_unused_lanes = true,
  25                 .clk_req = CLK_REQ0,
  26                 .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
  27         },
  28         { /* SD */
  29                 .engine_type = PCIE_ENGINE,
  30                 .port_present = true,
  31                 .start_logical_lane = 1,
  32                 .end_logical_lane = 1,
  33                 .link_speed_capability = GEN3,
  34                 .device_number = PCI_SLOT(SD_DEVFN),
  35                 .function_number = PCI_FUNC(SD_DEVFN),
  36                 .link_aspm = ASPM_L1,
  37                 .link_aspm_L1_1 = false,
  38                 .link_aspm_L1_2 = false,
  39                 .turn_off_unused_lanes = true,
  40                 .clk_req = CLK_REQ1,
  41                 .gpio_group_id = GPIO_69,
  42                 .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
  43         },
  44         { /* WWAN */
  45                 .engine_type = UNUSED_ENGINE,
  46                 .port_present = true,
  47                 .start_logical_lane = 2,
  48                 .end_logical_lane = 2,
  49                 .link_speed_capability = GEN3,
  50                 .device_number = PCI_SLOT(WWAN_DEVFN),
  51                 .function_number = PCI_FUNC(WWAN_DEVFN),
  52                 .link_aspm = ASPM_L1,
  53                 .link_aspm_L1_1 = true,
  54                 .link_aspm_L1_2 = true,
  55                 .turn_off_unused_lanes = true,
  56                 .clk_req = CLK_REQ2,
  57                 .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
  58         },
  59         { /* NVME */
  60                 .engine_type = PCIE_ENGINE,
  61                 .port_present = true,
  62                 .start_logical_lane = 4,
  63                 .end_logical_lane = 7,
  64                 .link_speed_capability = GEN3,
  65                 .device_number = PCI_SLOT(NVME_DEVFN),
  66                 .function_number = PCI_FUNC(NVME_DEVFN),
  67                 .link_aspm = ASPM_L1,
  68                 .link_aspm_L1_1 = true,
  69                 .link_aspm_L1_2 = true,
  70                 .turn_off_unused_lanes = true,
  71                 .clk_req = CLK_REQ3,
  72                 .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
  73         },
  74         { /* Dummy Device */
  75                 .engine_type = PCIE_ENGINE,
  76                 .port_present = true,
  77                 .start_logical_lane = 8,
  78                 .end_logical_lane = 11,
  79                 .device_number = PCIE_GPP_BRIDGE_2_DEV,
  80                 .function_number = PCIE_GPP_2_4_FUNC,
  81                 .turn_off_unused_lanes = true,
  82                 .clk_req = CLK_REQ5,
  83                 .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
  84         },
  85         { /* Dummy Device */
  86                 .engine_type = PCIE_ENGINE,
  87                 .port_present = true,
  88                 .start_logical_lane = 16,
  89                 .end_logical_lane = 23,
  90                 .device_number = PCIE_GPP_BRIDGE_1_DEV,
  91                 .function_number = PCIE_GPP_1_0_FUNC,
  92                 .turn_off_unused_lanes = true,
  93                 .clk_req = CLK_REQ6,
  94                 .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
  95         }
  96 };
  97
  98 static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = {
  99         { /* DDI0 - eDP */
 100                 .connector_type = DDI_EDP,
 101                 .aux_index = DDI_AUX1,
 102                 .hdp_index = DDI_HDP1
 103         },
 104         { /* DDI1 - HDMI */
 105                 .connector_type = DDI_HDMI,
 106                 .aux_index = DDI_AUX2,
 107                 .hdp_index = DDI_HDP2
 108         },
 109         { /* DDI2 */
 110                 .connector_type = DDI_UNUSED_TYPE,
 111                 .aux_index = DDI_AUX3,
 112                 .hdp_index = DDI_HDP3,
 113         },
 114         { /* DDI3 - DP (type C) */
 115                 .connector_type = DDI_DP,
 116                 .aux_index = DDI_AUX3,
 117                 .hdp_index = DDI_HDP3,
 118         },
 119         { /* DDI4 - DP (type C) */
 120                 .connector_type = DDI_DP,
 121                 .aux_index = DDI_AUX4,
 122                 .hdp_index = DDI_HDP4,
 123         }
 124 };
 125
 126 void __weak variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors)
 127 {
 128 }
 129
 130 void __weak variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors)
 131 {
 132 }
 133
 134 void mainboard_get_dxio_ddi_descriptors(
 135                 const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
 136                 const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
 137 {
 138         /* Get Variant specific SD AUX Reset GPIO */
 139         guybrush_czn_dxio_descriptors[SD].gpio_group_id = variant_sd_aux_reset_gpio();
 140
 141         /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it
 142            is enabled. */
 143         if (is_dev_enabled(DEV_PTR(gpp_bridge_2)))
 144                 guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE;
 145
 146         if (variant_has_pcie_wwan())
 147                 guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18;
 148
 149         variant_update_dxio_descriptors(guybrush_czn_dxio_descriptors);
 150         variant_update_ddi_descriptors(guybrush_czn_ddi_descriptors);
 151
 152         *dxio_descs = guybrush_czn_dxio_descriptors;
 153         *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors);
 154
 155         *ddi_descs = guybrush_czn_ddi_descriptors;
 156         *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors);
 157 }