src/mainboard/google/hatch/variants/helios/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <commonlib/helpers.h>
   7
   8 static const struct pad_config gpio_table[] = {
   9         /* A8  : PEN_GARAGE_DET_L (wake) */
  10         PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
  11         /* A10 : FPMCU_PCH_BOOT1 */
  12         PAD_CFG_GPO(GPP_A10, 0, DEEP),
  13         /* A11 : PCH_SPI_FPMCU_CS_L */
  14         PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
  15         /* A12 : FPMCU_RST_ODL */
  16         PAD_CFG_GPO(GPP_A12, 0, DEEP),
  17         /* A18 : ISH_GP0 ==> NC */
  18         PAD_NC(GPP_A18, NONE),
  19         /* A19 : ISH_GP1 ==> NC */
  20         PAD_NC(GPP_A19, NONE),
  21         /* A20 : ISH_GP2 ==> NC */
  22         PAD_NC(GPP_A20, NONE),
  23         /* B19 : GSPI1_CS0# ==> NC */
  24         PAD_NC(GPP_B19, NONE),
  25         /* C1  : SMBDATA ==> NC */
  26         PAD_NC(GPP_C1, NONE),
  27         /* C4  : TOUCHSCREEN_DIS_L */
  28         PAD_CFG_GPO(GPP_C4, 0, DEEP),
  29         /* C6  : GPP_C6 ==> NC */
  30         PAD_NC(GPP_C6, NONE),
  31         /* C7  : GPP_C7 ==> NC */
  32         PAD_NC(GPP_C7, NONE),
  33         /* C23 : UART2_CTS# ==> NC */
  34         PAD_NC(GPP_C23, NONE),
  35         /* D5  : ISH_I2C0_SDA ==> NC */
  36         PAD_NC(GPP_D5, NONE),
  37         /* D6  : ISH_I2C0_SCL ==> NC */
  38         PAD_NC(GPP_D6, NONE),
  39         /* D7  : ISH_I2C1_SDA ==> NC */
  40         PAD_NC(GPP_D7, NONE),
  41         /* D8  : ISH_I2C1_SCL ==> NC */
  42         PAD_NC(GPP_D8, NONE),
  43         /* D9  : EN_PP3300_DX_TOUCHSCREEN */
  44         PAD_CFG_GPO(GPP_D9, 1, DEEP),
  45         /* D10 : ISH_SPI_CLK ==> EN_PP3300_PP1800_FP */
  46         PAD_CFG_GPO(GPP_D10, 0, DEEP),
  47         /* D15 : TOUCHSCREEN_RST_L */
  48         PAD_CFG_GPO(GPP_D15, 1, DEEP),
  49         /* D16 : USI_INT_L */
  50         PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
  51         /* D21 : SPI1_IO2 ==> NC */
  52         PAD_NC(GPP_D21, NONE),
  53         /* F0  : GPP_F0 ==> NC */
  54         PAD_NC(GPP_F0, NONE),
  55         /* F1  : GPP_F1 ==> NC */
  56         PAD_NC(GPP_F1, NONE),
  57         /* F3  : GPP_F3 ==> MEM_STRAP_3 */
  58         PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
  59         /* F10 : GPP_F10 ==> MEM_STRAP_2 */
  60         PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
  61         /* F11 : EMMC_CMD ==> NC */
  62         PAD_NC(GPP_F11, NONE),
  63         /* F20 : EMMC_RCLK ==> NC */
  64         PAD_NC(GPP_F20, NONE),
  65         /* F21 : EMMC_CLK ==> NC */
  66         PAD_NC(GPP_F21, NONE),
  67         /* F22 : EMMC_RESET# ==> NC */
  68         PAD_NC(GPP_F22, NONE),
  69         /* G0  : GPP_G0 ==> NC  */
  70         PAD_NC(GPP_G0, NONE),
  71         /* G1  : GPP_G1 ==> NC  */
  72         PAD_NC(GPP_G1, NONE),
  73         /* G2  : GPP_G2 ==> NC  */
  74         PAD_NC(GPP_G2, NONE),
  75         /* G3  : GPP_G3 ==> NC  */
  76         PAD_NC(GPP_G3, NONE),
  77         /* G4  : GPP_G4 ==> NC  */
  78         PAD_NC(GPP_G4, NONE),
  79         /* G5  : GPP_G5 ==> NC  */
  80         PAD_NC(GPP_G5, NONE),
  81         /* G6  : GPP_G6 ==> NC  */
  82         PAD_NC(GPP_G6, NONE),
  83         /* H3  : SPKR_PA_EN */
  84         PAD_CFG_GPO(GPP_H3, 1, DEEP),
  85         /* H4  : I2C2_SDA ==> NC */
  86         PAD_NC(GPP_H4, NONE),
  87         /* H5  : I2C2_SCL ==> NC */
  88         PAD_NC(GPP_H5, NONE),
  89         /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */
  90         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  91         /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */
  92         PAD_CFG_GPO(GPP_H14, 1, PLTRST),
  93         /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */
  94         PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
  95         /* H22 : MEM_STRAP_1 */
  96         PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
  97 };
  98
  99 const struct pad_config *override_gpio_table(size_t *num)
 100 {
 101         *num = ARRAY_SIZE(gpio_table);
 102         return gpio_table;
 103 }
 104
 105 /*
 106  * GPIOs configured before ramstage
 107  * Note: the Hatch platform's romstage will configure
 108  * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
 109  * as inputs before it reads them, so they are not
 110  * needed in this table.
 111  */
 112 static const struct pad_config early_gpio_table[] = {
 113         /* B15 : H1_SLAVE_SPI_CS_L */
 114         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 115         /* B16 : H1_SLAVE_SPI_CLK */
 116         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
 117         /* B17 : H1_SLAVE_SPI_MISO_R */
 118         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 119         /* B18 : H1_SLAVE_SPI_MOSI_R */
 120         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 121         /* C8  : UART_PCH_RX_DEBUG_TX */
 122         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 123         /* C9  : UART_PCH_TX_DEBUG_RX */
 124         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 125         /* C14 : BT_DISABLE_L */
 126         PAD_CFG_GPO(GPP_C14, 0, DEEP),
 127         /* PCH_WP_OD */
 128         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 129         /* C21 : H1_PCH_INT_ODL */
 130         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 131         /* C22 : EC_IN_RW_OD */
 132         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 133         /* E1  : M2_SSD_PEDET */
 134         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 135         /* E5  : SATA_DEVSLP1 */
 136         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 137         /* F2  : MEM_CH_SEL */
 138         PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
 139 };
 140
 141 const struct pad_config *variant_early_gpio_table(size_t *num)
 142 {
 143         *num = ARRAY_SIZE(early_gpio_table);
 144         return early_gpio_table;
 145 }
 146
 147 /*
 148  * Default GPIO settings before entering non-S5 sleep states.
 149  * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
 150  * This guarantees that A12's native3 function is disabled.
 151  * See https://review.coreboot.org/c/coreboot/+/32111 .
 152  */
 153 static const struct pad_config default_sleep_gpio_table[] = {
 154         PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 155 };
 156
 157 /*
 158  * GPIO settings before entering S5, which are same as
 159  * default_sleep_gpio_table but also, turn off FPMCU.
 160  */
 161 static const struct pad_config s5_sleep_gpio_table[] = {
 162         PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
 163         PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
 164 };
 165
 166 const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 167 {
 168         if (slp_typ == ACPI_S5) {
 169                 *num = ARRAY_SIZE(s5_sleep_gpio_table);
 170                 return s5_sleep_gpio_table;
 171         }
 172         *num = ARRAY_SIZE(default_sleep_gpio_table);
 173         return default_sleep_gpio_table;
 174 }
 175
 176 /* GPIOs needed to be set in romstage. */
 177 static const struct pad_config romstage_gpio_table[] = {
 178         /* Enable touchscreen, hold in reset */
 179         /* D9  : EN_PP3300_DX_TOUCHSCREEN */
 180         PAD_CFG_GPO(GPP_D9, 1, DEEP),
 181         /* D15 : TOUCHSCREEN_RST_L */
 182         PAD_CFG_GPO(GPP_D15, 0, DEEP),
 183 };
 184
 185 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 186 {
 187         *num = ARRAY_SIZE(romstage_gpio_table);
 188         return romstage_gpio_table;
 189 }