src/mainboard/google/hatch/variants/kohaku/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <baseboard/gpio.h>
   5 #include <soc/cnl_memcfg_init.h>
   6 #include <string.h>
   7
   8 static const struct cnl_mb_cfg baseboard_memcfg = {
   9         /*
  10          * The dqs_map arrays map the SoC pins to the lpddr3 pins
  11          * for both channels.
  12          *
  13          * "The index of the array is CPU byte number, the values are DRAM byte
  14          * numbers." - doc #573387
  15          *
  16          * the index = pin number on SoC
  17          * the value = pin number on lpddr3 part
  18          */
  19         .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4},
  20         .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4},
  21
  22         .dq_map[DDR_CH0] = {
  23                 {0xf, 0xf0},
  24                 {0x0, 0xf0},
  25                 {0xf, 0xf0},
  26                 {0xf, 0x0},
  27                 {0xff, 0x0},
  28                 {0xff, 0x0}
  29         },
  30         .dq_map[DDR_CH1] = {
  31                 {0xf, 0xf0},
  32                 {0x0, 0xf0},
  33                 {0xf, 0xf0},
  34                 {0xf, 0x0},
  35                 {0xff, 0x0},
  36                 {0xff, 0x0}
  37         },
  38
  39         /* Kohaku uses 200, 80.6 and 162 rcomp resistors */
  40         .rcomp_resistor = {200, 81, 162},
  41
  42         /* Kohaku Rcomp target values */
  43         .rcomp_targets = {100, 40, 40, 23, 40},
  44
  45         /* Set CaVref config to 0 for LPDDR3 */
  46         .vref_ca_config = 0,
  47
  48         /* Disable Early Command Training */
  49         .ect = 0,
  50 };
  51
  52 void variant_memory_params(struct cnl_mb_cfg *bcfg)
  53 {
  54         memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
  55 }